Skhynix Inc.

Hynix Semiconductor Inc.

Keon Soo Shim

Yoo Nam Jeon

Bong Yeol Park

Keun Woo Lee

Hee Joung Park

Sang Heon Lee

Hae Soon Oh

Byung In Lee

Jae Il Tak

Ki Jun Kim

Eun Seok Choi

Ki Seog Kim

Ju Yeab Lee

Sung Kee Park

Hyun Seung Yoo

Hee Sik Park

Seul Ki Oh

Yong Mook Baek

Jong Soon Leem

Bong Kil Kim

A method for operating a memory device includes providing a memory block including at least one source select transistor coupled between a source line and a bit line, a plurality of memory cells, and a drain select transistor, controlling a source select line coupled to the at least one source select transistor and a plurality of word lines coupled to the plurality of memory cells to be in a floating state, and applying an erase voltage to the source line and the bit line.

Memory device having improved program and erase operations and operating method of the memory device

A memory device includes a memory cell array having a plurality of memory blocks sharing a source line, a peripheral circuit for performing a program operation and an erase operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit. The control logic controls the peripheral circuit such that some source select transistors adjacent to the source line among a plurality of source select transistors included in an unselected memory block among the plurality of memory blocks are floated in a source line precharge operation during the program operation.

A semiconductor device includes a memory cell array including a vertical channel layer, two or more selection transistors, and a plurality of memory cells formed along the vertical channel; a peripheral circuit suitable for programming the two or more selection transistors and the memory cells; and a control circuit suitable for controlling the peripheral circuit to decrease a pass voltage applied to one word line adjacent to two or more selection lines coupled to the respective selection transistors, during a program operation in which the peripheral circuit applies a program voltage to the two or more selection lines and applies the pass voltage to a plurality of word lines connected to the memory cells.

Semiconductor device and methods of manufacturing and operating the same

The semiconductor device may include a first sub-pipe gate having a pipe hole formed therein; a second sub-pipe gate disposed on the first sub-pipe gate and passed-through by vertical holes being coupled to the pipe hole, wherein a material of the second sub-pipe gate has a lower oxidation rate than that of a material of the first sub-pipe gate; a first oxidized layer formed within a portion of the first sub-pipe gate to conform to a contour of the pipe hole; and a second oxidized layer formed within a portion of the second sub-pipe gate to conform to a contour of the vertical holes and the contour of the pipe hole.

Memory device having a pipe transistor and sub-pipe gate materials with different oxidation rates

A semiconductor device includes a memory array including memory blocks; and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the program loop is performed by controlling a target threshold voltage value of the selection transistors based on a difference between a cell current value of the selected memory block and a reference cell current value.

Semiconductor device and operating method thereof

A semiconductor device includes a memory array including memory blocks, and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the operation circuit performs the program loop on the selection transistors so that a difference occurs between threshold voltages of the selection transistors and a target threshold voltage based on a difference between a cell current value of the selected memory block and a reference cell current value.

A semiconductor device according to an embodiment may include a memory string including a drain selection transistor, memory cells and a source selection transistor all coupled between a bit line and a common source line, and the drain selection transistor, the memory cells and the source selection transistor configured to operate, respectively, in response to voltages applied to a drain selection line, word lines and a source selection line. The semiconductor device may include an operation circuit configured for performing a program operation. The operation circuit may be configured for sequentially performing a first operation, a second operation, and a third operation. In the first operation memory cells adjacent to the drain selection transistor may be programmed. In the second operation memory cells adjacent to the source selection transistor may be programmed. In the third operation remaining memory cells may be programmed.

Semiconductor device

A semiconductor memory device and a method of operating the same are provided. The device may include a memory cell array including a plurality of memory blocks and a peripheral circuit configured for selecting one of the plurality of memory blocks and performing a program operation on selected memory cells of the selected memory block when the program operation is performed. The peripheral circuit may be configured to float a plurality of source select lines and a plurality of drain select lines of an unselected memory block of the plurality of memory blocks when the program operation is performed.

Semiconductor memory device improving threshold voltage of unselected memory block and method of operating the same

A semiconductor device may include memory blocks having a plurality of strings including drain select transistors and memory cells electrically coupled in series between a bit line and a pipe transistor and source select transistors and memory cells electrically coupled in series between a common source line and the pipe transistor; a circuit group configured to float drain select lines electrically coupled to the drain select transistors included in unselected memory blocks and source select lines electrically coupled to the source select transistors included in the unselected memory blocks and to ground a pipe line electrically coupled to the pipe transistor when a program operation of a selected memory block among the memory blocks is performed; and a control circuit configured to control the circuit group.

Semiconductor device, semiconductor system having the same and operating method thereof

Disclosed are a semiconductor memory device, a memory system including the same, and an operating method thereof. The memory system includes: a semiconductor memory device including a plurality of memory chips; and a controller configured to measure a cell current of each of the plurality of memory chips, generate temperature compensation data corresponding to the measured cell current, and store the generated temperature compensation data in each of the plurality of memory chips.

Semiconductor memory device, memory system including the same, and operating method thereof

The semiconductor memory device includes a memory cell block including a plurality of memory cells, a peripheral circuit section configured to perform an erase loop including a supply operation supplying an erase voltage and an erase verification operation to erase data stored in the memory cells, a fail bit counter configured to count the number of memory cells not erased in an erase operation among the memory cells to generate a count signal based on a fail count corresponding to a counting result in the erase verification operation, and a controller configured to control the peripheral circuit section to set a new erase voltage by increasing an erase voltage, used in a previous erase loop, by a first step voltage or decreasing the erase voltage by a second step voltage based on the fail count, and perform the erase loop using the new erase voltage.

Semiconductor memory device and method of operating the same

A memory device comprises a drain select line, a source select line, word lines, and a string connected between a bit line and a common source line. A program-inhibited voltage is applied to the bit line and a first voltage of a positive potential is applied to the drain select line. A second voltage for activating a programmed memory cell is applied to a word line to which the programmed memory cell is connected. A programming operation is performed by applying a program voltage to a selected word line and applying a pass voltage to the unselected word lines.

Programming method of flash memory device

A nonvolatile memory device including a bit line voltage supply unit configured to supply a power source voltage, a second voltage in which a second reference voltage has been subtracted from a third reference voltage, or a third voltage in which a first reference voltage has been subtracted from the third reference voltage according to data stored in a first latch unit, a second latch unit, and a third latch unit included in a page buffer, and a bit line voltage setting unit configured to transfer a voltage of 0 V or an output voltage of the bit line voltage supply unit to a bit line according to the data stored in the first, second, and third latch units.

Nonvolatile memory device and method of programming the same

A memory device capable of enlarging an interval between a source selection transistor and a memory cell adjacent to the source selection transistor, enlarging an interval between a drain selection transistor and a memory cell adjacent to the drain selection transistor, or enlarging the intervals between the source selection transistor and the memory cell adjacent to the source selection transistor and between the drain selection transistor and the memory cell adjacent to the drain selection transistor, prevents the memory cell adjacent to the source or drain selection transistor from being degraded in programming speed due to program disturbance.

Growing community of inventors

Gyeonggi-do, South Korea

Keon Soo Shim