Advanced Micro Devices Corporation

Other

Fujitsu Corporation

Kenneth W Au

Arvind Halliyal

Mark T Ramsbey

Robert B Ogle

Hideki Komori

Yu Nan Sun

Tuan Duc Pham

David Keating Foote

Steven K Park

Fei Wang

Bharath Rangarajan

Susan G Kim

A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the formation of a nitrogenated top oxide layer. The process includes the sequential formation of a silicon nitride layer and a top oxide layer using an in-situ LPCVD or RTCVD deposition process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. After forming the top oxide layer, an annealing process is carried out to diffuse nitrogen into the top oxide layer. The formation of a nitrogenated top oxide layer provides an improved two-bit EEPROM memory device by reducing charge leakage in the ONO floating-gate electrode.

Nitridation process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device

Methods and arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The methods and arrangements effectively reduce the severity of the topology attributable to the space between adjacent floating gates, by advantageously reducing the thickness of the floating gates. The altered topology allows a subsequently formed control gate to be formed without significant surface depressions. Significant surface depressions in the control gate can lead to cracks in the silicide layer that is formed on the control gate. The cracking usually occurs during subsequent thermal processing of the semiconductor device. Thus the disclosed methods and arrangements prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.

Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices

A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the formation of a top oxide layer using a high-temperature-oxide (HTO) deposition process in which the HTO process is carried out at a temperature of about 700 to about 800&deg; C. by either an LPCVD or RTCVD deposition processor. The process further includes the sequential formation of a silicon nitride layer and a top oxide layer using an in-situ LPCVD or RTCVD deposition process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. The formation of the top oxide layer using an HTO deposition process provides an improved two-bit EEPROM memory device by reducing charge leakage in the ONO floating-gate electrode.

High temperature oxide deposition process for fabricating an ONO floating-gate electrode in a two bit EEPROM device

A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes providing a semiconductor substrate and thermally growing a first silicon oxide layer overlying the semiconductor substrate. A thermal anneal is performed after growing the first silicon oxide layer in an ambient atmosphere of at least one of nitric oxide, nitrous oxide and ammonia. In this regard, nitrogen is incorporated into the first silicon oxide layer which leads to a better performance and a higher quality of the ONO structure. A silicon nitride layer is formed to overlie the first silicon oxide layer; and a second layer of silicon oxide is formed to overlie the silicon nitride layer to complete the ONO structure.

Method of fabricating an ONO dielectric by nitridation for MNOS memory cells

A process for fabricating a MONOS type Flash cell device having a periphery field oxide region and a bit-line region includes providing a semiconductor substrate and growing a barrier silicon oxide layer to overlie semiconductor substrate. Thereafter, a thick silicon nitride layer is formed to overlie the barrier silicon oxide layer. A mask and etch are performed at the periphery of the MONOS type cell to form a trench in the semiconductor substrate. The periphery field oxide region is formed by depositing silicon oxide to fill the trench. Thereafter, a mask and etch are performed at the core of the MONOS cell to form a trench in the semiconductor substrate. The bit-line oxide region is formed by depositing silicon oxide to fill the trench. Thereafter, the thick silicon nitride layer is removed. Since the periphery field oxide region and bit-line region are formed before the thick nitride layer is removed, the formation of an unwanted bird's beak is reduced.

Method of using source/drain nitride for periphery field oxide and bit-line oxide

A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the formation of a first and second oxide layers using a high-temperature-oxide (HTO) deposition process in which the HTO process is carried out at a temperature of about 700 to about 800&deg; C. The process further includes the sequential formation of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer using an RTCVD process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. The formation of the first and second oxide layers using an RTCVD process provides an improved two-bit EEPROM memory device by reducing charge leakage in the ONO floating-gate electrode.

Process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device using rapid-thermal-chemical-vapor-deposition

A process for fabricating an ONO structure for a MONOS type Flash cell having a core and a periphery includes providing a semiconductor substrate. A first silicon oxide layer is grown overlying the semiconductor substrate, and a silicon nitride layer is deposited overlying the silicon oxide layer. Before depositing a second silicon oxide layer of the ONO structure, a bit-line mask is performed for forming at least one bit-line at the core. Thereafter, an ONO mask is formed to protect the ONO structure during an etch of the periphery. After depositing and cleaning the masks for the bit-line formation and the periphery etch, the second silicon oxide layer is deposited to overlie the silicon nitride layer using an HTO deposition process. By depositing the second silicon oxide layer after forming the ONO and bit-line masks, degradation of the second silicon oxide layer is prevented, and the top silicon oxide layer maintains a high quality.

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Fremont, CA, United States of America

Kenneth W Au