International Business Machines Corporation

Infineon Technologies Ag

Infineon Technologies North America Corp.

Globalfoundries Inc.

Kenneth T Settlemyer, Jr

Kangguo Cheng

Carl John Radens

Ravikumar Ramachandran

Ramachandra Divakaruni

Michael Patrick Chudzik

Rajarao Jammy

Jochen C Beintner

Yujun Li

Timothy Joseph Dalton

Dirk Pfeiffer

Helmut Horst Tews

Katherina E Babich

Oh-Jung Kwon

Deok-kee Kim

Harald F Okorn-Schmidt

Min-Soo Kim

Oleg Gluschenkov

Thomas W Dyer

Hiroyuki Akatsu

Stephan Kudelka

Joseph Francis Shepard, Jr

Arpan Pravin Mahorowala

James Allan Bruce

Russell Herbert Arndt

Glenn Walton Gale

Padraic C Shafer

Jack Allan Mandelman

Haining S Yang

Dureseti Chidambarrao

Johnathan E Faltermeier

Christopher Carr Parks

William Alfred Syverson

Jacek G Smolinski

Frederick William Kern, Jr

Irene Lennox McStay

Radhika Srinivasan

Daria Rose Dooling

Ralph James Williams

James J Toomey

Richard O Henry

Porshia Shane Wrschka

James Hannah

Kathryn H Varian

Stephen D Thomas

Porshia S Parkinson

Arpan P Mohorowala

Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

Methods and structures for protecting one area while processing another area on a chip

Solutions for diagnosing in-line critical dimension control adjustments in a lithographic process are disclosed. In one embodiment, a method includes: locating a control structure in a data set representing one of a chip or a kerf; simulating component dimensions within a region proximate to the control structure; determining a difference between the simulated component dimensions within the region and target component dimensions within the region; determining whether the difference exceeds a predetermined tolerance threshold; adjusting a simulation condition in response to determining the difference exceeds the predetermined tolerance threshold; and repeating the simulating of the component dimensions within the region, the determining of the difference, and the determining of whether the difference exceeds the predetermined tolerance threshold in response to the adjusting of the simulation condition.

Diagnosing in-line critical dimension control adjustments using optical proximity correction verification

Solutions for accounting for photomask deviations in a lithographic process during optical proximity correction verification are disclosed. In one embodiment, a method includes: identifying a wafer control structure in a data set representing one of a first chip or a kerf; biasing the data set representing the first chip in the case that the wafer control structure is in the data set representing the first chip; biasing the data set representing the kerf or a second chip distinct from the first chip, in the case that the wafer control structure is in the data set representing the kerf or the second chip; simulating formation of the wafer control structure; determining whether the simulated wafer control structure complies with a target control structure; and iteratively adjusting an exposure dose condition in the case that the simulated wafer control structure does not comply with the target control structure.

Optical proximity correction verification accounting for mask deviations

A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.

Device fabrication by anisotropic wet etch

A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent to the bottom of the trench; forming an oxidized layer of the substrate in the bottom region of the trench; and removing the oxidized layer of the substrate from the bottom region of the trench, a cross-sectional area of the lower region of the trench greater than a cross-sectional area of the upper region of the trench.

Method of fabricating a bottle trench and a bottle trench capacitor

A method is presented for fabricating a non-planar field effect device. The method includes the production of a Si based material Fin structure that has a top surface substantially in parallel with a {111} crystallographic plane of the Si Fin structure, and the etching of the Si Fin structure with a solution which contains ammonium hydroxide (NHOH). In this manner, due to differing etch rates in ammonium hydroxide of various Si based material crystallographic planes, the corners on the Fin structure become clipped, and angles between the horizontal and vertical planes of the Fin structure increase. A FinFET device with clipped, or rounded, corners is then fabricated to completion. In a typical embodiment the FinFET device is selected to be a silicon-on-insulator (SOI) device.

Corner clipping for field effect devices

A method of forming a vertical DRAM device. A lower trench is filled with polycrystalline or amorphous semiconductor for a capacitor. An upper trench portion has exposed sidewalls of single-crystal semiconductor. The method then includes etching the single-crystal semiconductor sidewalls to widen the upper trench portion beyond the exposed upper surface of the semiconductor fill of the capacitor to form exposed regions of single-crystal semiconductor on a bottom portion of the upper trench adjacent to the exposed upper surface of the semiconductor fill. A trench top insulating layer is deposited on the bottom portion of the upper trench, over the upper surface of the semiconductor fill and over the adjacent regions of single-crystal semiconductor. The method then includes forming a vertical gate dielectric layer, wherein the trench top insulating layer extends below the vertical gate insulating layer.

Method for etching single-crystal semiconductor selective to amorphous/polycrystalline semiconductor and structure formed by same

A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files by a host machine such that the files correspond to regions of interest or partitions with defined margins, dispersing the partitioned data files to available cpus within the network, processing of each job by the cpu receiving the file, wherein artifacts arising from bisection of partitioning margins during the partitioning, including cut-induced false errors, are detected and removed, and the shape-altering effects of such artifact errors are minimized and transmitting the results of processing at each cpu to the host machine for aggregate processing.

Method and apparatus for parallel data preparation and processing of integrated circuit graphical design data

A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners.

Pattern enhancement by crystallographic etching

The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.

Selective etching to increase trench surface area

A field effect transistor formed by a sacrificial gate process has a simplified process and improved yield by using a tunable resistant anti-reflective coating (TERA) as the cap layer over the sacrificial gate layer. The TERA layer serves as a tunable anti-reflection layer for photolithography patterning, a hardmask for etching the sacrificial gate, a polish stopping layer for planarization, and a blocking layer for preventing silicide formation over the sacrificial gate. The TERA is stripped by a two-step process that is highly selective to the nitride spacers, so that the spacers are not damaged in the process of stripping the sacrificial gate.

Replacement gate with TERA cap

Growing community of inventors

Poughquag, NY, United States of America

Kenneth T Settlemyer, Jr