Texas Instruments Corporation

Fujikura Limited

Texas Instruments Japan Limited

Other

Kenji Masumoto

Mutsumi Masumoto

Masatoshi Inaba

Nobuyuki Sadakata

Masahiro Kaizu

Akihito Kurosaka

Takanao Suzuki

Kensho Murata

Tadanori Ominato

Bernardo Gallegos

Makoto Yoshino

Akira Karashima

Takashi Nakashima

Sreenivasan Kalyani Koduri

Masazumi Amagai

Katsumi Yamaguchi

Tomohiro Okazaki

A method for forming a packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least one land pad thereon and a first dielectric layer positioned lateral to the land pad and a non-die attach region. A second dielectric layer is formed on the top substrate surface of the package substrate. An IC die which is mounted to the top substrate surface of the package substrate. An underfill layer is formed between the IC die and the die attach region.

Packaged electronic devices having die attach regions with selective thin dielectric layer

A packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least one land pad thereon and a first dielectric layer positioned lateral to the land pad and a non-die attach region. The non-die attach region includes a second dielectric layer, wherein a thickness of the second dielectric layer is&#x3e;a thickness of the first dielectric layer by at least 5 &#x3bc;m. An IC die has a top semiconductor surface including active circuitry and at least one bonding conductor formed on the top semiconductor surface, and a bottom surface, wherein the bonding conductor of the IC die is joined to the land pad of the package substrate. An underfill layer is between the IC die and the die attach region.

A semiconductor device assembly can include a semiconductor chip, a receiving substrate, and a spacer structure interposed between the semiconductor chip and the receiving substrate. The spacer provides an unoccupied space between a pillar and a bond finger for excess conductive material, which can otherwise flow from between the pillar and bond finger and result in a conductive short. The spacer can also provide an offset between the pillar and bond finger.

Copper pillar bonding for fine pitch flip chip devices

In one aspect, the invention provides a semiconductor device that comprises a semiconductor device packaging substrate core. A first interconnect structure is located within a mold region and on a die side of the substrate core and has a first conductive metal density associated therewith. A second interconnect structure is located within the mold region and on a solder joint side of the substrate core and has a second conductive metal density associated therewith, wherein the second conductive metal density within the mold region is about equal to or less than the first conductive metal density within the mold region.

Semiconductive device having improved copper density for package-on-package applications

A semiconductor deviceThe device includes an interposerhaving two major surfaces. The first surfaceincludes patterned metal conductors and bond padsand the second surface includes an array of solder ballsThe device includes a semiconductor chiphaving a top surface and a back surface, the back surface of the chip adjacent the interposerand the top surface including a plurality of terminals. Also included is a layer of polymeric materialdisposed on the first surfaceof the interposer covering the area of the interposer over the solder ball array. At least a portion of the polymeric layer is between the chipand the interposerThe device further includes a plurality of electrical connectionsbetween the chip terminals and the bond padson the interposer.

Package for a semiconductor device

An insulating layer () having an opening portion () at a position conformable to an electrode pad () is formed. Next, a resin projection portion () is formed on the insulating layer (). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (), the resin projection portion () and the region sandwiched therebetween. A Cu plating layer () is formed by electrolytic copper plating, using the resist film as a mask.

Method for producing a semiconductor package, with a rerouted electrode formed on a resin projection portion

Semiconductor package, semiconductor device and electronic device

An apparatus comprising an integrated circuit structure is provided. The integrated circuit structure comprises a substrate and a photoreceiver. The substrate has a first side and a second side opposite the first side and includes a first light passage area operable to allow light to pass through. The photoreceiver has an aperture located on a first side of the photoreceiver and is flip-chip mounted to the substrate such that the first side of the photoreceiver faces the second side of the substrate. The photoreceiver is operable to translate light signals received through the aperture into digital signals and to transmit the digital signals. The first light passage area is aligned with the aperture of the photoreceiver such that the light signals may be received through the light passage area and into the aperture of the photoreceiver.

Integrated circuit structure having a flip-chip mounted photoreceiver

A semiconductor device. The device includes an interposerhaving two major surfaces. The first surfaceincludes patterned metal conductors and bond pads, and the second surface includes an array of solder balls. The device includes a semiconductor chiphaving a top surface and a back surface, the back surface of the chip adjacent the interposer, and the top surface including a plurality of terminals. Also included is a layer of polymeric materialdisposed on the first surfaceof the interposer covering the area of the interposer over the solder ball array. At least a portion of the polymeric material layer is between the chipand the interposer. The device further includes a plurality of electrical connectionsbetween the chip terminals and the bond padson the interposer.

Package for semiconductor device having a device-supporting polymeric material covering a solder ball array area

Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor device related to this invention contains each of the processes that form a wiring () for the purpose of electrically connecting each electrode pad () and external connecting terminals on top of a wafer () on which semiconductor elements are formed, connect conductive balls that are preformed by a separate process on top of this, and next, cover the above-mentioned wafer with a resin () such that the upper portion of the conductive supporting posts () are exposed. In a later process, solder balls () are arranged as external connecting terminals on the upper portion of the conductive supporting posts, and in the final process, semiconductor elements are formed by dicing the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements.

Semiconductor device and its manufacturing method

An insulation film for providing an insulation substrate carrying a semiconductor chip of a semiconductor package. Insulation filmis provided with rows of opposing sprocket holesformed on either edge of the above mentioned insulation film, and through holesare disposed two-dimensionally between the rows of sprocket holes. Pitch p between through holesis determined by the relationship mp=nL (i.e., n and m are integers, and n&#x3c;m), wherein pitch of the sprocket holes is taken to be L. Through holesare selectively utilized during formation of the desired circuit pattern upon insulation filmaccording to size of the manufactured semiconductor package.

Semiconductor package insulation film and manufacturing method thereof

An insulation film for providing an insulation substrate carrying a semiconductor chip of a semiconductor package. Insulation filmis provided with rows of opposing sprocket holesformed on either edge of the above mentioned insulation film, and through holesare disposed two-dimensionally between the rows of sprocket holes. Pitch p between through holesis determined by the relationship m p=n L (i.e., n and m are integers, and n&#x3c;m), wherein pitch of the sprocket holes is taken to be L. Through holesare selectively utilized during formation of the desired circuit pattern upon insulation filmaccording to size of the manufactured semiconductor package.

An insulating layer ( ) having an opening portion ( ) at a position conformable to an electrode pad ( ) is formed. Next, a resin projection portion ( ) is formed on the insulating layer ( ). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion ( ), the resin projection portion ( ) and the region sandwiched therebetween. A Cu plating layer ( ) is formed by electrolytic copper plating, using the resist film as a mask.

Semiconductor package, semiconductor device, electronic device, and method of manufacturing semiconductor package

A method to realize low-profile semiconductor devices by grinding a resin sealed block and realize level grinding by eliminating warpage of the resin sealed block. Semiconductor devices are produced by step (B) in which multiple semiconductor chips are mounted face down onto the surface of substrate , step (C) in which molding resin is injected onto substrate in order to form resin sealed block in which multiple semiconductor chips are sealed, step (E) in which resin sealed block is cut halfway from the side of substrate , and step (F) in which resin sealed block is ground from the side of molding resin in order to separate it into individual semiconductor devices

Growing community of inventors

Hiji-machi, Japan

Kenji Masumoto