Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Materials Corporation

Mitsubishi Materials Silicon Corporation

Kenji Kusakabe

Yoshiko Kokawa

Tohru Koyama

Katsuhiko Tamura

Yasuna Nakamura

Izuru Naito

Makoto Imura

Masahiro Sekine

Yoshihiko Konishi

Yoshio Inasawa

Shigeru Makino

Toshiyuki Horie

Keiji Yamauchi

Shinji Kuroda

Syuji Nuimura

A reflector antenna device includes: an auxiliary reflectorthat receives an electric wave radiated from an opening portion by a primary radiatorand reflects the electric wave; and a main reflectorthat receives the electric wave that is reflected by the auxiliary reflectorand radiates the electric wave to a space. In the reflector antenna device, the configurations of the auxiliary reflectorand the main reflectorare designed such that an electric power in an area of the main reflectorwhere the auxiliary reflectoris projected on the main reflectorin parallel with the radiating direction of the electric wave due to the main reflectoris equalor lower than a predetermined first threshold value, and a radiation pattern of the antenna which is determined by the area of the main reflectorother than the area has a desired characteristic.

Reflector antenna

In order to lessen the deterioration of the VSWR, a plural-reflector antenna system is provided wherein an appropriately shaped vertex matching plate is disposed on the subreflector and electric waves that reenter the primary radiator are cancelled out. The electric waves radiated from the primary radiator are reflected by the subreflector and are radiated into space after being reflected by the main reflector. The passing area in the horn aperture, through which the reflected waves from the vertex matching plate pass, is made to be analogous to the aperture of the primary radiator, by defining the vertex matching plate as an ellipsoid, and by orienting its minor-axis direction in the major-axis direction of the main reflector and its major-axis direction, in the minor-axis direction of the main reflector.

Plural-reflector antenna system

The present invention is mainly characterized in that a semiconductor substrate improved so as to maintain a gettering effect for a long time can be obtained. A polycrystalline silicon film is formed on the rear surface of a semiconductor substrate. A silicon oxide film and silicon nitride film are formed over the rear surface of semiconductor substrate so as to cover polycrystalline silicon film.

Method of making a semiconductor substrate having gettering effect

A silicon wafer having a low concentration of carbon and a silicon wafer having a high concentration of carbon are joined and polished to prescribed thicknesses to form a semiconductor substrate according to the present invention.

Semiconductor substrate having a gettering layer

Silicon substrate is provided with silicon single-crystalline wafer, natural oxide film and poly-crystalline silicon film. The thickness of natural oxide film is controlled to be less than 10 .ANG.. Since the thickness of natural oxide film is made less than 10 .ANG., heavy metals travel smoothly from silicon single-crystalline wafer to poly-crystalline silicon film in the process of gettering. In other words, it is possible to enhance gettering effect.

Method of manufacturing semiconductor device with a gettering sink

A semiconductor substrate allowing reduction of crystal defects in a device formation region of an epitaxial silicon layer and allowing control of the amount of internal precipitation defects of the single crystal silicon substrate, a method of manufacturing such semiconductor substrate, and a semiconductor device utilizing such semiconductor substrate are disclosed. The semiconductor substrate includes a single crystal silicon substrate, an epitaxial silicon layer, and a polycrystalline silicon layer. The interstitial oxygen concentration of the single crystal silicon substrate is set within the range of 12.5-14.0.times.10.sup.17 (atoms/cm3) according to the old ASTM specification. The epitaxial silicon layer is formed on the top surface of the single crystal silicon substrate. The polycrystalline silicon layer is formed at least on the rear surface of the single crystal silicon substrate to a thickness of at least 1 .mu.m.

Semiconductor substrate for bipolar element

A semiconductor device without erroneous operation and deterioration of characteristics in a transistor even when an impurity region is formed in self-alignment by ion implantation using a gate electrode as a mask, and a method of manufacturing thereof are disclosed. This semiconductor device includes a gate electrode formed of a polycrystal silicon layer 4b having the crystal orientation of the crystal grains arranged in a definite orientation. By implanting ions at a predetermined angle with respect to the crystallographic axis of the crystal grains of the polycrystal silicon layer 4b in forming a p.sup.+ impurity region 5 by ion implantation using the gate electrode as a mask, the channeling phenomenon where ions pass through the gate electrode is prevented. Therefore, generation of erroneous operation and deterioration of characteristics in a transistor are prevented in forming an impurity region in self-alignment by ion implantation using the gate electrode as a mask.

Semiconductor device having a gate electrode of polycrystal layer and a

Semiconductor device with a gettering sink material layer

A silicon wafer having a low concentration of oxygen and a silicon wafer having a high concentration of oxygen are joined and polished to prescribed thicknesses to form a semiconductor substrate according to the present invention. A region formed of the wafer having a low concentration of oxygen is used as a region where an element is formed, and a region formed of the wafer having a high concentration of oxygen produces a gettering effect on metal impurities and defects. As a DZ layer having a low concentration of oxygen, a wafer manufactured by an MCZ method or a wafer manufactured by a CZ method is used after being heat-treated at high temperature to diffuse oxygen outward. In another example, a damage layer, a polycrystalline silicon layer, an amorphous silicon layer or the like is formed between a DZ layer and an IG layer.

A semiconductor device not aggravated in transistor characteristic even when an impurity region is formed by ion implantation using a gate electrode as a mask, and a method of manufacturing thereof are disclosed. The semiconductor device includes a gate electrode 10 implemented by a polycrystal silicon layer 4 having the crystal orientation of the crystal grains thereof arranged in a predetermined orientation, and a single crystal silicon layer 5 formed on the polycrystal silicon layer 4 having a crystal orientation identical to that of the polycrystal silicon layer 4. The channelling phenomenon in which B.sup.+ ions pass through to beneath the gate electrode 10 is prevented in forming an impurity region 6 by ion implantation to obtain a semiconductor device that does not have the characteristic of the formed transistor aggravated.

Method of manufacturing semiconductor device having a two layered

Semiconductor device having a two layered structure gate electrode

A semiconductor production apparatus employs a target prepared by using a solder alloy which has a limited Sn content. The solder alloy can form an alloy layer having large elongation between a metal target and a backing plate to prevent undesirable cracking and separation of target, whereby a semiconductor device can be produced with a high degree of reliability.

Semiconductor production apparatus

A silicon wafer for a semiconductor substrate comprises a flat wafer body, with a polycrystalline silicon layer formed only on the rear surface of said wafer body. The silicon wafer is manufactured by the steps of forming a polycrystalline silicon layer on the entire surface of the silicon wafer body, etching and removing the portion of the polycrystalline silicon layer which is formed on the side surface of silicon wafer body, and polishing and removing the polycrystalline silicon layer on the front surface of the silicon wafer body.

Growing community of inventors

Hyogo, Japan

Kenji Kusakabe