Keysight Technologies, Inc.

Kenichi Takano

Hiroshi Nada

Sumio Shimonishi

Motochika Juso

A wafer test system includes a cabinet housing multiple instruments, a test head having multiple pin modules, and cable connecting at least some of the instruments to the pin modules. The cabinet has at least one front door, left and right side panels, a rear door, a ceiling unit, and a bottom unit. Each of the instruments has a front surface, left and right side surfaces, and a rear surface. At least some of the instruments each include at least one first connection terminal. The cabinet further includes a first space defined between the at least one front door and the front surface of each of the instruments, and a second space defined between the rear door and the front surface of each of the instruments. The first space and the second space are separated in the cabinet to separate intake air and exhaust air of the instruments.

Semiconductor wafer test system

Systems and methods for determining a capacitance on a device-under-test ('DUT'). An example implementation includes a voltage signal generator that generates a voltage signal alternating between a high voltage and a low voltage at regular time intervals. The voltage signal generator causes a DUT current to flow in the DUT. The DUT current comprises a leakage current and a capacitance measurement current in response to the voltage signal. A current signal generator receives the DUT current from the DUT. The current signal generator generates a cancellation current signal alternating between high and low values at the regular time intervals of the voltage signal such that the cancellation current signal cancels the leakage current through the DUT. A signal measurement circuit receives the capacitance measurement current remaining after the leakage current is canceled to generate an output voltage having an output voltage value used to determine a capacitance of the DUT.

Growing community of inventors

Hino, Japan

Kenichi Takano