Kabushiki Kaisha Toshiba

Kenichi Otsuka

Kazuya Mori

Mari Otsuka

Akihiro Kajita

Kei Watanabe

Akifumi Gawase

Hitoshi Itoh

Johta Fukuhara

Tomonori Kitakura

Katsuhiko Oya

A method of fabricating a semiconductor device according to one embodiment includes: forming an interlayer sacrificial film and an insulating film located thereon above a semiconductor substrate having a semiconductor element, the interlayer sacrificial film having a wiring provided therein; etching the insulating film, or, etching the insulating film and the interlayer sacrificial film to form a trench reaching the interlayer sacrificial film; forming a gas permeable film in the trench; gasifying and removing the interlayer sacrificial film through the trench and the gas permeable film; and forming a sealing film on the gas permeable film for sealing the vicinity of an opening of the trench after removing the interlayer sacrificial film.

Method of fabricating semiconductor device

Disclosed are an apparatus and a method for manufacturing a semiconductor device. A Si wafer set within an L/UL chamber is transferred under the state of a high vacuum through a transfer chamber into a Ti chamber. The wafer is heated to at least 300&deg; C. within the Ti chamber by a heating mechanism arranged within the Ti chamber. Then, a TiSi,film is formed at a bottom portion of a contact hole by a plasma CVD method using an Ar gas supplied through a gas line as a carrier gas and a TiCl,gas supplied through another gas line as a source gas, Ti in the source gas being self-aligned with Si in the wafer. The wafer having the TiSi,film formed therein is transferred through the transfer chamber into a W chamber without being exposed to the air atmosphere. Within the W chamber, a W film is consecutively deposited by a selective CVD method on the TiSi,film. The particular technique makes it possible to form the TiSi,film of a high quality at a bottom portion of the contact hole even if the contact hole has a large aspect ratio.

Apparatus and method for manufacturing a semiconductor device having a multi-wiring layer structure

This invention provides a method of manufacturing a semiconductor device, including the steps of forming an insulating film and a first metal film on one major surface of a semiconductor substrate, each of the insulating film and the first metal film having a partially exposed surface, and selectively forming a second metal film on the exposed surface of the first metal film, wherein formation of the second metal film is performed in an atmosphere containing a gasified silicon compound obtained upon gasifying a liquid silicon compound containing at least one element selected from the group consisting of carbon, hydrogen, oxygen, chlorine, and fluorine, or its reaction product, whereby the exposed surface of the insulating film is chemically modified with the silicon compound or its reaction product.

Method of manufacturing a semiconductor device

In a method of manufacturing a semiconductor device having a multilayer wiring structure, it has at least two underlying layers having different etching conditions. Firstly, the native oxide film formed on one of the underlying layers, or a barrier metal layer, is etched out under etching conditions suitable for the barrier metal layer. Then, the surface of the barrier metal layer is capped with a plugging material having etching conditions similar to or substantially the same as those of the other one of the underlying layers, or a lower wiring layer. Subsequently, the native oxide film and the etching by-product formed on the lower wiring layer are etched out under etching conditions suitable for the lower wiring layer. Thereafter, contact holes for the two underlying layers are buried with a conductive substance to establish electric connection with their respective upper conductive layers. With the above described steps, the entire manufacturing process is significantly simplified and the time required for burying the contact holes is greatly reduced without remarkably increasing the contact resistance between the barrier metal layer and the lower wiring layer and the respective buried conductive substances.

Method of manufacturing semiconductor device having a multilayer wiring

An Al alloy interconnection layer is deposited on a silicon oxide layer, and a first carbon layer is formed on the Al alloy interconnection layer. Then, the first carbon layer and the Al alloy interconnection layer are patterned, thereby forming a first interconnection layer consisting of the Al alloy interconnection layer and the first carbon layer. Sequentially, a second carbon layer is formed on the first interconnection layer and the silicon oxide layer. The second carbon layer is entirely etched by the RIE method, thereby leaving the second carbon layer only on side surfaces of the first interconnection layer. A high temperature layer made of SiO.sub.2 is deposited on the second carbon layer, the first interconnection layer and the silicon oxide layer. Thereafter, the high temperature layer is etched back until the first carbon layer is exposed, thus being flattened. An interlayer insulating layer is deposited on the high temperature layer and the first interconnection layer.

Method of manufacturing a semiconductor device having multi-layered

An inter-level insulation film is formed on a first-level interconnection layer and part of the inter-level insulation film which lies on the first-level interconnection layer is etched to form a contact hole. After a natural oxidation film formed on the surface of part of the first-level interconnection layer which is exposed in the contact hole is removed, the resultant structure is exposed to a gas atmosphere containing halogen to purify the surface of the inter-level insulation film. After this, a contact plug is deposited and formed on the first-level interconnection layer which is exposed in the contact hole by the selective CVD method to fill in the contact hole. A second-level interconnection layer is formed on the inter-level insulation film and the first-level and second-level interconnection layers are electrically connected to each other via the contact plug.

Contact plug forming method

Method of manufacturing a semiconductor device having reliable

A gas purification apparatus has two gas purification units which are alternately operated. A gas purification capacity measuring means includes a means including valves for separating a target gas purification unit from a line, an evacuating means for evacuating the separated gas purification unit at a high vacuum, a means including a supply tank for supplying a predetermined very small amount of an impurity gas to an inlet of the high-vacuum separated gas purification unit, an auxiliary tank (e.g., a pressure reduction tank, a metering tank, and a pressure reduction valve), and a vacuum gauge for measuring a change in pressure at the outlet upon supply of the impurity gas to the inlet. In the gas purification apparatus having gas purification units each incorporating a getter material, the gas purification capacity of each gas purification unit can be more accurately and easily measured.

Growing community of inventors

Kawasaki, Japan

Kenichi Otsuka