Sharp Kabushiki Kaisha Corporation

Kenichi Azuma

Akio Kawamura

Katsuji Iguchi

Shinichi Sato

Takuji Tanigami

Toshihisa Gotoh

Kouichi Takeuchi

Akiyoshi Mutoh

A semiconductor device includes a first insulating layer and a second insulating layer in a trench. The first insulating layer insulates two MOSFETs from each other, and the second insulating layer has a true stress opposite to a true stress of the first insulating layer. The second insulating layer includes two regions of different true stresses. This enables a drain current flow in each MOSFET to be independently controlled in a semiconductor device that employs a STI method for element isolation.

Semiconductor device and fabrication method thereof

A semiconductor device has a structure that reduces the parasitic capacitance by using a film with a low relative dielectric constant as the side wall material of the gate. The material with a low relative dielectric constant is preferably a material whose relative dielectric constant is less than the relative dielectric constant of an oxide film, i.e., less than about 3.9.

Semiconductor device having a low dielectric constant film and manufacturing method thereof

Process for producing semiconductor device

A process for manufacturing a non-volatile semiconductor memory device by forming a tunnel dielectric film, a floating gate electrode, an interlayer capacitive film and a control gate electrode successively on a semiconductor substrate includes introducing nitrogen atoms into at least one of an interface between the floating gate electrode and the interlayer capacitive film and an interface between the interlayer capacitive film and the control gate electrode.

Process for manufacturing non-volatile semiconductor memory device by

In a semiconductor device manufacturing method, when an impurity is implanted into a region for forming an impurity diffused layer in a silicon substrate, or into a polysilicon layer formed on the silicon substrate, the injection of the impurity is carried out through a protective film, such as a TiN film, which contains no oxygen and which is selectively removable from silicon. Thereafter, an annealing for activating the impurity thus implanted is applied so that an impurity diffused layer is formed, and the protective film is removed. Subsequently, a refractory metal film is adhesively provided on the silicon surface of the region where the impurity diffused layer is formed, and reaction between the silicon and the refractory metal film is caused by an annealing so that a refractory metal silicide film is formed. With this arrangement, it is possible to produce a semiconductor device which has a refractory metal silicide film having a low resistance.

Method for manufacturing semiconductor device

An MOS transistor comprises a semiconductor substrate having a field region; a gate electrode formed on the semiconductor substrate through the intermediatry of a gate insulating film; and source/drain regions formed in the semiconductor substrate; wherein the field region including at least a lower insulating film and an upper insulating film made of a material permitting the upper insulating film to be selectively etched with respect to the lower insulating film; the gate electrode being configured such that the gate length of a top surface thereof is greater than the gate length of a bottom surface thereof facing a channel region positioned between the source/drain regions; the gate electrode having a sidewall spacer formed of a sidewall insulating layer made of the lower insulating film and a material permitting the sidewall insulating layer to be selectively etched with respect to the upper insulating film, the sidewall spacer contacting a side wall of the gate electrode for covering an outer periphery of the channel region; and the channel region being substantially leveled with the source/drain regions.

MOS transistor and fabrication process therefor

A process for manufacturing a semiconductor device which comprises the following steps of (i) forming a first insulating film on the whole surface of a semiconductor substrate having thereon a thin conductive layer with an intervening gate insulating film, (ii) removing the first insulating film at a channel region to cause the thin conductive layer to be exposed, thereby forming an opening portion, (iii) implanting ions in the opening portion to form a channel region in the substrate, (iv) forming a gate electrode of a conductive material in the opening portion, (v) removing only the first insulating film with leaving the gate electrode as it is and then implanting ions by using the gate as a mask to form a low carrier density region in the substrate, (vi) layering a second insulating film on the substrate including the gate and then carrying out an anisotropic etching to build a sidewall of the gate electrode, and (vii) implanting ions by use of the gate electrode and its sidewall as a mask to form a high carrier density region on the substrate, whereby completing an insulating gate type of field effect transistor having a low carrier density region for mitigating field effect, the low carrier density region adjoining to source and drain regions of high carrier density.

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Tenri, Japan

Kenichi Azuma