Industrial Technology Research Institute

Mediatek Corporation

Keng-Li Su

Pei-Ling Tseng

Chih-Sheng Lin

Chih-Wen Hsiao

Chia-Pao Chang

Chih Sheng Lin

Min-Chuan Wang

Shyh-Shyuan Sheu

Chin-Sheng Lin

Chen-Pang Kung

Wei-Jen Chang

Zhe-Hui Lin

Kuang-Chung Tao

Ting-Yuan Cheng

Hsin-Chi Lai

Chieh-Sheng Chen

Ching-Sheng Lin

Jan-Ruel Lin

Yung-Hue Chen

A through silicon via (TSV) repair circuit of a semiconductor apparatus is provided. The TSV repair circuit includes a first chip, at least one second chip, at least two TSVs, at least two data path circuits, and an output logic circuit. Each data path circuit includes an input driving circuit, a short-circuit detection circuit, a bias circuit, and a leakage current cancellation circuit. The input driving circuit transforms an input signal into a pending signal and transmits the pending signal to a first terminal of the corresponding TSV. The short-circuit detection circuit detects a short circuit between the corresponding TSV and a silicon substrate according to the input signal and the first terminal of the TSV and generates a short-circuit detection output signal. The leakage current cancellation circuit prevents a leakage current produced by a first level voltage from entering the silicon substrate according to the short-circuit detection output signal.

Through silicon via repair circuit of semiconductor apparatus

A through silicon via (TSV) repair circuit is provided. The TSV repair circuit includes at least two transmission control switches and at least two transmission path modules. Two transmission control switches transmit an input signal of a first chip or a second chip to one of two terminals in each of the transmission path modules according to a switch signal. Each transmission path module includes at least two data path circuits and corresponding TSVs. Each data path circuit includes an input driving circuit, a short-circuit detection circuit and a leakage current cancellation circuit. The short-circuit detection circuit detects whether to detect whether short-circuit on the TSV and a silicon substrate is present and generate a short-circuit detection output signal. The leakage current cancellation circuit to avoid a leakage current generated by a first level voltage to flow into the silicon substrate according to the short-circuit detection output signal.

Through silicon via repair circuit

TSV repair circuit of a semiconductor device includes a first chip, a second chip, at least two TSV, at least two data path circuits and an output logic circuit. Each data path circuit comprises an input driving circuit, a TSV detection circuit, a memory device, a protection circuit and a power control circuit. The TSV detection circuit detects a TSV status, the memory device keeps the TSV status, the protection circuit determines whether to pull a first end of the TSV to a ground voltage according to the TSV status, and the power control circuit prevents a leakage current of a power voltage from flowing through a substrate.

Through silicon via repair circuit of semiconductor device

A monitoring method of a three-dimensional integrated circuit (3D IC) is provided, wherein the method includes: providing a plurality of TSVs, providing a plurality of inverters; connecting the inverters with the plurality of TSVs as a circuit loop; enabling the circuit loop to oscillate; measuring an output signal on an output end of one of the plurality of inverters; and determining the manufacturing state of the plurality of TSVs of the 3D IC based on the output signal and apparatus using the same.

Monitoring method for three-dimensional intergrated circuit (3D IC) and apparatus using the same

A TSV bidirectional repair circuit of a semiconductor apparatus is provided. The bidirectional repair circuit includes a first and a second bidirectional switches and at least two transmission path modules. The first and the second bidirectional switches determine whether to transmit an input signal of a first chip or a second chip to each of the transmission path modules according to a switch signal. Each transmission path module includes at least two data path circuits and corresponding TSVs. Each data path circuit includes an input driving circuit, a short-circuit detection circuit and a leakage current cancellation circuit. The short-circuit detection circuit detects whether short-circuit on the corresponding TSV and a silicon substrate is present according to the input signal and the corresponding TSV to produce a short-circuit detection output signal.

Through silicon via bidirectional repair circuit of semiconductor apparatus

A multi-chip stack structure including a first chip, a second chip, a shielding layer, and a plurality of conductive bumps is provided. The second chip is stacked on the first chip. The second chip has a plurality of through silicon via (TSV) structures to conduct a reference voltage. The shielding layer and the plurality of conductive bumps are disposed between the first chip and the second chip, and are electrically connected to the plurality of TSV structures. The shielding layer can isolate noises and improve signal coupling between two adjacent chips.

Multi-chip stack structure

A monitoring method for Through-Silicon Vias (TSVs) of a three-dimensional integrated circuit (3D IC) is provided, wherein the 3D IC includes a plurality of TSVs, and the method includes: providing a plurality of inverters; connecting the inverters with the TSVs as a circuit; enabling the circuit to oscillate; measuring an output signal on an output end of one of the inverters; and determining the characteristic of TSVs of the 3D IC based on the output signal.

Monitoring method for through-silicon vias of three-dimensional intergrated circuit (3D IC) and apparatus using the same

An electrostatic discharge (ESD) structure for a 3-dimensional (3D) integrated circuit (IC) through-silicon via (TSV) device is provided. The ESD structure includes a substrate, a TSV device which is formed through the substrate and is equivalent to a resistance-inductance-capacitance (RLC) device, and at least one ESD device which is disposed in the substrate and electrically connected to one end of the TSV device. The ESD structure can protect the 3D IC TSV device.

Electrostatic discharge structure for 3-dimensional integrated circuit through-silicon via device

A memory with improved write current is provided, including a bit line, a write switch and a control circuit. The write switch is coupled between a voltage source and the bit line, and has a control terminal. Based on a bit line select signal, the control circuit controls the electric conductance of the write switch and discharges/charges the parasitic capacitors of the write switch. The voltage source is turned on after the control terminal of the write switch reaches a pre-determined voltage level.

Memories with improved write current

The invention provides a multi-state sense amplifier, coupled to at least one memory cell and a plurality of reference cells. The source follower, coupled between a first node and the output terminal of the memory cell, clamps the voltage drop across the memory cell to generate a memory cell current flowing through the first node. The source follower circuit, coupled between a plurality of second nodes and the output terminals of the reference cells, clamps the voltage drops across the reference cells to generate a plurality of reference currents respectively flowing through the second nodes. The current mirror circuit, coupled to the first node and the second nodes, duplicates the memory cell current of the first node to affect the reference currents on the second nodes, thereby generating a memory cell voltage on the first node and a plurality of reference voltages on the second nodes.

Memory and multi-state sense amplifier thereof

A memory structure and data writing method thereof includes a power supply circuit and a bridge circuit. The bridge circuit is driven by the power supply circuit, and operate in a plurality of conduction modes. The memory structure only requires one set of power supply circuit and does not need to know the resistance of the bit line in advance, also the signal error is hardly occurred when the memory structure is switching between positive and negative.

Memory structure and data writing method thereof

The invention provides a multi-state sense amplifier, coupled to at least one memory cell with changeable resistance and a plurality of reference cells. The first current mirror circuit, coupled to the output terminal of the memory cell, generates a second memory cell current at a first node according to a first memory cell current through the memory cell. The second current mirror circuit, coupled to the output terminal of the reference cells, generates a plurality of second reference currents at a plurality of second nodes according to a plurality of first reference currents through the reference cells. The load circuit, coupled to the first node, the second nodes, and a ground, provides equal loads for the second memory cell current and the second reference currents to respectively generate a memory cell voltage at the first node and a plurality of reference voltages at the second nodes.

Multi-state sense amplifier

The invention relates to a sense amplifier comprising the following element: a first current mirror unit coupled to a high voltage source, outputting a first current and a second current according to a first reference current, wherein the second current is twice the first current; a second current mirror unit coupled to a high voltage source, outputting a third current according to a second reference current; a first impedor coupled to the second current and a low voltage source; a second impedor coupled to the third current and a low voltage source; a third current mirror coupled to the first, second and third currents, and the first current is regarded as the reference current of the third current mirror unit, thus, the current which flows through the first impedor is the first current, and the current which flows through the second impedor is a fourth current.

Sense amplifier

A memory array including a plurality of programmable memory cells, a plurality of column lines and a plurality of row lines is introduced. Each of the programmable memory cells is coupled to corresponding one of the column lines and corresponding one of the row lines. Each of the programmable memory cells includes an organic memory cell and an active switching element. The active switching element is controlled by the column line and interposed between the row line and the organic memory cell. Under controlling of the column line, the active switching element is turned on to coupling the row line and the organic memory cell to connect to each other.

Programmable memory cell and operation method

An upconverter for mixing a single-ended RF signal with a differential local oscillator signal to generate a differential IF signal, that includes a source degenerated first differential pair comprising matched first and second transistors, each having source, gate and drain terminals, wherein the gate of the first transistor receives the input signal and the gate of the second transistor receives a ground potential, and a second differential pair comprising matched third and fourth transistors, each having source, gate and drain terminals, and a third differential pair comprising matched fifth and sixth transistors, each having source, gate and drain terminals, wherein the sources of the third and fourth transistors are coupled to the drain of the first transistor and the sources of the fifth and sixth transistors are coupled to the drain of the second transistor, the gate of the third transistor is coupled to the gate of the fifth transistor and the gate of the fourth transistor is coupled to the gate of the sixth transistor, the drain of the third transistor is coupled to the drain of the sixth transistor and the drain of the fourth transistor is coupled to the drain of the fifth transistor, the gates of the third and fourth transistors receive the differential local oscillator signal, the drains of the third and fourth transistors supply the differential IF signal, the gate of the first transistor is coupled to the single-ended RF signal, and the gate of the second transistor is coupled to a DC control signal.

Growing community of inventors

Hsinchu, Taiwan

Keng-Li Su