Qualcomm Incorporated

Kendrick H Yuen

Wenqing Wu

Seung Hyuk Kang

Jung Pill Kim

Raghu Sagar Madala

Xia Li

Xiaochun Zhu

Robert P Gilmore

Abhishek Banerjee

Senthil Kumar Govindaswamy

Peiyuan Wang

William Xia

Matthew Michael Nowak

Lindsay A Weaver, Jr

Jeffrey Alexander Levin

Todd Robert Sutton

David Merrill Jacobson

David W Hansquine

Farrokh Khatibi

Nicholas K Yu

Chengzhi Pan

Jeff A Levin

Houtan Dehesh

Eric L Henderson

Zhenyu Sun

Sean Li

Richard Larson

William H Xia

A memory cell includes an elongated first electrode coupled to a magnetic tunnel junction (MTJ) structure and an elongated second electrode aligned with the elongated first electrode coupled to the MTJ structure. The elongated electrodes are configured to direct mutually additive portions of a switching current induced magnetic field through the MTJ. The mutually additive portions enhance switching of the MTJ in response to application of the switching current.

STT-MRAM design enhanced by switching current induced magnetic field

A method and apparatus for generating random binary sequences from a physical entropy source having a state A and a state B by detecting whether the physical entropy source is in the state A or in the state B, attempting to shift the state of the physical entropy source to the opposite state in a probabilistic manner with less than 100% certainty, and producing one of four outputs based on the detected state and the state of the physical entropy source before the attempted shift. The outputs are placed in first and second queues and extracted in pairs from each queue. Random binary bits are output based on the sequences extracted from each queue.

Method and apparatus for generating random numbers using a physical entropy source

A magnetic tunneling junction non-volatile register with feedback for robust read and write operations. In an embodiment, two MTJ devices are configured to store a logical 0 or a logical 1, and are coupled to drive an output node to a voltage indicative of the stored logical 0 or a logical 1. The output of a D flip-flop is fed to the two MTJ devices so that the state of the D flip-flop may be stored in the two MTJ devices during a store operation. During a read operation, the D flip-flop outputs the state of the two MTJ devices. Read disturbances are mitigated with the use of an edge detector coupled to the output node, so that a LOW voltage is provided to the D flip-flop if a rising voltage at the output node is detected.

Magnetic tunneling junction non-volatile register with feedback for robust read and write operations

Embodiments of the disclosure are directed to generating a random number. An embodiment of the disclosure passes a current from a read operation through a magnetic tunnel junction (MTJ) to cause a first magnetization orientation of a free layer to switch to a second magnetization orientation, the switch in magnetization orientation causing a change in a resistance of the MTJ, and periodically samples the resistance of the MTJ to generate a bit value for the random number.

Magnetic tunnel junction based random number generator

Sensor circuitry including probabilistic switching devices, such as spin-transfer torque magnetic tunnel junctions (STT-MTJs), is configured to perform ultra-low power analog to digital conversion and compressive sensing. The analog to digital conversion and compressive sensing processes are performed simultaneously and in a manner that is native to the devices due to their probabilistic switching characteristics.

Spin torque transfer magnetic tunnel junction intelligent sensing

A multi-free layer magnetic tunnel junction (MTJ) cell includes a bottom electrode layer, an anti-ferromagnetic layer on the bottom electrode layer, a fixed magnetization layer on the anti-ferromagnetic layer and a barrier layer on the fixed magnetization layer. A first free magnetization layer is on a first area of the barrier layer, and a capping layer is on the first free magnetization layer. A free magnetization layer is on a second area of the barrier layer, laterally displaced from the first area, and a capping layer is on the second free magnetization layer. Optionally current switches establish a read current path including the first free magnetization layer concurrent with not establishing a read current path including the second free magnetization layer. Optionally current switches establishing a read current path including the first and second free magnetization layer.

Multi-free layer MTJ and multi-terminal read circuit with concurrent and differential sensing

Clock signals are distributed on a chip by applying an oscillating magnetic field to the chip. Local clock generation circuits including magnetic field sensors are distributed around the chip and are coupled to local clocked circuitry on the chip. The magnetic field sensors may include clock magnetic tunnel junctions (MTJs) in which a magnetic orientation of the free layer is free to rotate in the free layer plane in response to the applied magnetic field. The MTJ resistance alternates between a high resistance value and a low resistance value as the free layer magnetization rotates. Clock generation circuitry coupled to the clock MTJs senses voltage oscillations caused by the alternating resistance of the clock MTJs. The clock generation circuitry includes amplifiers, which convert the sensed voltage into local clock signals.

Clock distribution using MTJ sensing

A probabilistic programming current is injected into a cluster of bi-stable probabilistic switching elements, the probabilistic programming current having parameters set to result in a less than unity probability of any given bi-stable switching element switching, and a resistance of the cluster of bi-stable switching elements is detected. The probabilistic programming current is injected and the resistance of the cluster state detected until a termination condition is met. Optionally the termination condition is detecting the resistance of the cluster of bi-stable switching elements at a value representing a multi-bit data.

Method and apparatus of probabilistic programming multi-level memory in cluster states of bi-stable elements

A packet switching architecture provides for a switch system comprised of a cellular base station in communication with the PSTN through a switch. Data packets are routed through the switch system as necessary to effect communication between the public switched telephone network (PSTN) and mobile radiotelephones disposed within the cellular coverage area surrounding the base station. A packet interconnection subsystem operates to transfer data packets between a plurality of interface ports, to which are coupled a corresponding plurality of signal lines. Within the interconnection subsystem, one or more distribution/consolidation (DISCO) interface units are mutually coupled together through a central router unit. Each DISCO interface unit is configured to consolidate the data packets received through at least two signal ports onto a consolidation bus, as well as to distribute the addressed data packets from a distribution bus to two or more of ports. In a preferred implementation, the interconnection subsystem is realized so as to efficiently provide redundancy among the interface units within the interconnection network.

Method and apparatus for distribution/consolidation (DISCO) interface

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San Diego, CA, United States of America

Kendrick H Yuen