Sandisk Technologies Inc.

Sandisk Corporation

Broadcom Corporation

Ken Jian Ming Wang

Chih-Chin Liao

Han-Shiao Chen

Hem P Takiar

Chin-Tien Chiu

Cheemen Yu

Cheeman Yu

Rezaur Rahman Khan

Shrikar Bhagath

Jack Chang Chien

Matthew Vernon Kaufmann

Ming Wang Sze

A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.

Printed circuit board with coextensive electrical connectors and contact pad areas

A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.

Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging

A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

Hidden plating traces

A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.

Substrate panel with plating bar structured to allow minimum kerf width

Methods, systems, and apparatuses for integrated circuit packages, and for package stacking, are provided. An electrically conductive frame is attached to a first surface of a substrate. The electrically conductive frame includes a perimeter ring portion, a plurality of leads, and a plurality of interconnect members positioned within a periphery formed by the perimeter ring portion. Each interconnect member is coupled to the perimeter ring portion by a respective lead. A first end of each interconnect member is coupled to the first surface of the substrate. An encapsulating material is applied to the first surface of the substrate, without covering a second end of each interconnect member with the encapsulating material. The perimeter ring portion is removed from the electrically conductive frame to isolate the plurality of interconnect members. A first integrated circuit package is formed in this manner. A second integrated circuit package may be mounted to the first package. Signals of the first package may be electrically coupled with the second package at the exposed second ends of the interconnect members. Side surfaces of the interconnect members may be exposed at sides of the first package.

Integrated circuit package with etched leadframe for package-on-package interconnects

According to one exemplary embodiment, a lead frame package includes a number of leads and a number of contacts, where each of the contacts is situated over one of the leads. The lead frame package further includes a semiconductor die including a number of bond pads. Each of the contacts is directly attached and bonded to one of the bond pads on the semiconductor die. Each of the contacts is situated over a top portion of one of the leads, where the top portion has a shorter length than a middle portion of each of the leads. Each of the contacts is connected to one of the bond pads on the semiconductor die without a wire bond. The semiconductor die does not include a redistribution layer situated over an active surface of the semiconductor die.

Low cost lead frame package and method for forming same

According to one embodiment, a semiconductor die having increased usable area has at least six sides. The semiconductor die has a reduced stress at each corner of the die, resulting in smaller keep out zones near the corners of the semiconductor die, which allow the placement of bond pads near each corner of the die. The semiconductor die further allows the placement of active circuitry near each corner of the semiconductor die. One embodiment results in a 5.0% increase in usable area on the semiconductor die.

Semiconductor die having increased usable area

A semiconductor package having a low profile is disclosed. In embodiments, a surface mounted component may be mounted directly to the core of the semiconductor package substrate, so that there is no conductive layer, plating layers or solder paste between the component and the substrate core. The surface mounted component may be any type of component which may be surface mounted on a substrate according to an SMT process, including for example passive components and various packaged semiconductors.

Padless substrate for surface mounted components

Methods and apparatus for integrated circuit (IC) packages with improved thermal performance and input/output capabilities are described. An integrated circuit (IC) package includes a leadframe, an IC die, a substrate having opposing first and second surfaces, a first wirebond, and a second wirebond. The leadframe includes a die attach pad having opposing first and second surfaces and a plurality of leads that emanate in an outward direction from the die attach pad. The IC die is coupled to the first surface of the die attach pad. The substrate is coupled to the die attach pad. Contact pads on the first surface of the substrate are electrically connected to bond fingers on the second surface of the substrate. The first wirebond couples a first bond pad on a first surface of the IC die to a bond finger on the second surface of the substrate. The second wirebond couples a second bond pad on the first surface of the IC die to a lead of the plurality of leads.

Growing community of inventors

San Francisco, CA, United States of America

Ken Jian Ming Wang