Taiwan Semiconductor Manufacturing Comp. Ltd.

Ken-Hsien Hsieh

Ru-Gun Liu

Shih-Ming Chang

Chih-Ming Lai

Ming-Feng Shieh

Tsai-Sheng Gau

Yung-Sung Yen

Tsong-Hua Ou

Wen-Chun Huang

Huang-Yu Chen

Lee-Chung Lu

Yuan-Te Hou

Wen-Li Cheng

Wei-Liang Lin

Chih-Jie Lee

Jyu-Horng Shieh

Chun-Kuang Chen

Chia-Ying Lee

Dong-Yo Jheng

Chin-Hsiang Lin

Wen-Ju Preet Yang

Shuo-Yen Chou

Li-Chun Tien

Chin-Chang Hsu

Ming-Hui Chih

Ko-Bin Kao

Shau-Lin Shue

Chung-Ju Lee

Tien-I Bao

Burn Jeng Lin

Cheng-Hsiung Tsai

Yen-Chun Huang

Shih-Chun Huang

Fang-Yu Fan

Yu-Hsiang Kao

Ya Hui Chang

Chin-Hsiung Hsu

Ying-Yu Shen

HungLung Lin

Sheng-Min Wang

Wei-Shuo Su

Jiann-Tyng Tzeng

Shi Ning Ju

Shih-Wei Peng

Kuei-Shun Chen

Wei Min Chan

Ting Yu Chen

Hsin-Chih Chen

Gwan Sin Chang

Chin-Yuan Tseng

Chia-Ping Chiang

Yu-Po Tang

You-Cheng Xiao

Chen-Hau Wu

Pi-Tsung Chen

Wen-Hung Tseng

Hoi-Tou Ng

Wei-Long Wang

Pai-Wei Wang

Dio Wang

Yi-Yin Chen

Jhih-Jian Wang

Ching-Yu Chang

Hui-Zhong Zhuang

Xiangdong Chen

Dian-Hau Chen

Yi-Kan Cheng

Chi-Cheng Hung

Chi-Yu Lu

Jerry Chang Jui Kao

Hua-Tai Lin

Pin-Dai Sue

Chii-Ping Chen

Cheng-I Huang

Yu-Tien Shen

Yung-Chen Chien

Chien-Wen Lai

Joy Cheng

Yen-Sen Wang

Ming-Yi Lin

Ching Fu Chang

Meng-Wei Chen

Cheng Kun Tsai

Ta-Ching Yu

Ming-Jhih Kuo

Kuan-Hsin Lo

Hung Lung Lin

Wen Lo

Yu-Hsun Chen

Yu-Tse Lai

Chien Lin Ho

Chen-Hung Lu

Johnny Chiahao Li

Pai-Wei Wan

Meng-Tze Chen

Yu-Chin Huang

Li-Hsiang Lai

Shou-Yen Chou

Lee Fung Song

Manuel Alejandro Fernandez Lopez

The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.

Methods for integrated circuit design and fabrication

In a method of tool matching, aberration maps of two or more optical systems of two or more scanner tools are determined. A photoresist pattern is generated by projecting a first layout pattern by an optical system of each one of the two or more scanner tools on a respective substrate. One or more Zernike coefficients of the two or more optical systems are adjusted based on the determined aberration maps of the two or more optical systems to minimize critical dimension (CD) variations in a first region of the photoresist patterns on each respective substrate.

Tool mismatch reduction using aberration map of the tools

A first bright field reticle and a second bright field reticle are utilized for a double exposure EUV photolithography process in which exposure areas of the first and second bright field reticles overlap. The first and second reticles each include, respectively, a substrate, a reflective multilayer on the substrate, a main pattern of absorption material on the reflective multilayer, a black border area, and an additional absorption area of the absorption material between the black border and the main pattern.

Method and system to introduce bright field imaging at stitching area of high-NA EUV exposure

A semiconductor processing system includes a first photolithography system and a second photolithography system. The semiconductor processing system includes a layout database that stores a plurality of layouts indicating features to be formed in a wafer. The semiconductor processing system includes a layout analyzer that analyzes the layouts and selects either the first photolithography system or the second photolithography system based on dimensions of features in the layouts.

System and method for selecting photolithography processes

A semiconductor structure includes: a first gate structure and a second gate structure extending in a first direction; a first base level metal interconnect (M0) pattern extending in a second direction perpendicular to the first direction; a second M0 pattern extending in the second direction; a third M0 pattern located between the first and second gate structures and extending in the first direction, two ends of the third M0 pattern connected to the first M0 pattern and the second M0 pattern, respectively; a fourth M0 pattern and a fifth M0 pattern located between the first and second M0 patterns and extending in the second direction. A distance between the fourth M0 pattern and the first M0 pattern in the first direction is equal to a minimum M0 pattern pitch, and a distance between the fourth M0 pattern and the second M0 pattern is equal to the minimum M0 pattern pitch.

Two-dimensional (2D) metal structure and method of forming the same

In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.

Method of manufacturing semiconductor devices

A method includes receiving a layout for fabricating a mask, determining a plurality of target contours corresponding to a plurality of sets of lithographic process conditions, determining a modification to the layout, simulating the modification to the layout under the plurality of sets of lithographic process conditions to produce a plurality of simulated contours, determining a cost of the modification to the layout based on comparisons between the plurality of simulated contours and corresponding ones in the plurality of target contours, and providing the modification to the layout for fabricating the mask based at least in part on the cost being within a predetermined threshold.

Optical proximity correction and photomasks

A method includes forming a conductive member over a first conductive line; forming a second conductive line over the conductive member; and removing a portion of the conductive member exposed by the second conductive line to form a conductive via. The formation of the second conductive line is implemented prior to the formation of the conductive via. A semiconductor structure includes a first conductive line having a first surface; a second conductive line disposed above the first conductive line and having a second surface overlapping the first surface; and a conductive via electrically connected to the first surface and the second surface. The conductive via includes a first end disposed within the first surface, a second end disposed within the second surface, and a cross-section between the first end and the second end, wherein at least two of interior angles of the cross-section are substantially unequal to 90°.

Semiconductor structure and method for forming the same

A method comprises generating an original layout having main pattern sets; simulating a first energy distribution of the original layout on a pupil plane of a lithography system, wherein the first energy distribution has a first wavefront; generating a first modified layout by inserting dummy pattern sets in regions of the original layout that are not occupied by the main pattern sets; simulating a second energy distribution of the first modified layout on a pupil plane of a lithography system; determining whether a second wavefront of the simulated second energy distribution is more homogeneous than the first wavefront of the first energy distribution; and performing a first lithography process using a first photomask having the first modified layout in response to second wavefront of the simulated second energy distribution being determined as more homogeneous than the first wavefront of the first energy distribution.

Method for forming semiconductor device

A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.

Lithography process monitoring method

Two-dimensional (2D) metal structure

A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a patterning process; and forming a second plurality of trenches in the first layer by another patterning process, resulting in combined trench patterns in the first layer. A first trench of the second plurality connects two trenches of the first plurality. The method further includes forming dielectric spacer features on sidewalls of the combined trench patterns. A space between two opposing sidewalls of the first trench is completely filled by the dielectric spacer features and another space between two opposing sidewalls of one of the two trenches is partially filled by the dielectric spacer features.

Spacer etching process for integrated circuit design

A method includes receiving a layout for fabricating a mask, determining a first target contour corresponding to a first set of process conditions, determining a second target contour corresponding to a second set of process conditions, simulating a first potential modification to the layout under the first set of process conditions to generate a first simulated contour, simulating a second potential modification to the layout under the second set of process conditions to generate a second simulated contour, evaluating costs of the first and second potential modifications based on comparing the first and second simulated contours to the first and second target contours, respectively, and providing the layout and one of the first and second potential modifications having a lower cost for fabricating the mask. The first set of process conditions is different from the second set of process conditions.

In a method of manufacturing a semiconductor device, a trench pattern is formed in a first layer disposed over an underlying layer, and a first dimension of the trench pattern is reduced by first directional deposition. In the first directional deposition, a deposition rate on a first side wall of the trench pattern extending in a first axis is greater than a deposition rate on a second side wall of the trench pattern extending in a second axis crossing the first axis, the first axis and the second axis being horizontal and parallel to a surface of the underlying layer.

Growing community of inventors

Taipei, Taiwan

Ken-Hsien Hsieh