Intel Corporation

Kemal Aygun

Zhiguo Qian

Zhichao Zhang

Jianyong Xie

Henning Braunisch

Yidnekachew S Mekonnen

Yu Zhang

Yu Amos Zhang

Tolga Memioglu

Sujit Sharan

Tao Wu

Sanka Ganesan

Kaladhar Radhakrishnan

Srikant Nekkanty

Robert L Sankman

Kai Xiao

Dae-Woo Kim

Gong Ouyang

Johanna M Swan

Feras Eid

Telesphor Kamgaing

Srinivas V Pietambaram

Sasha N Oster

Omkar G Karhade

John Stephen Guzek

Eric Jin Li

Joshua Heppner

Gaurav Chawla

Gregorio R Murtagian

Daniel N Sobieski

Charles A Gealer

Ajay Jain

Jiwei Sun

Emile Davies-Venn

Cemil S Geyik

Adel A Elsherbini

Kristof Darmawikarta

Rahul N Manepalli

Nitin A Deshpande

Islam A Salama

Mathew J Manusharow

William J Lambert

Pooya Tadayon

Digvijay Ashokkumar Raorane

Rajasekaran Swaminathan

Mitul Bharat Modi

Jeffory L Smalley

Michael J Hill

Chung-Hao Chen

Jeff C Morriss

Kuang C Liu

Li-Sheng Weng

Glen Patrick Gordon

Drew W Delaney

Christopher J Nelson

Mohiuddin M Mazumder

Eric C Palmer

Eduard Roytman

Michael Garcia

Tyler N Osborn

Nevin Altunyurt

Chandrashekhar Ramaswamy

Kimberly Dawn Eilert

Sarah M Canny

Shawna M Liff

Ravindranath Vithal Mahajan

Saikumar Jayaraman

Shigeki Tomishima

Sri Ranga Sai Boyapati

Wilfred Gomes

Zuoguo Wu

Brandon C Marin

Kyu Oh Lee

Xiang Li

Ram S Viswanath

James Chris Matayabas, Jr

Ravi V Mahajan

Tarek A Ibrahim

Andrew Paul Collins

Brent Ryan Rothermel

Dong-Ho Han

Frank Patrick O'Mahony

Sriram Srinivasan

Stephen H Hall

Richard J Dischler

Beom-Taek Lee

Steven A Klein

Xiaohong Jiang

Jun Liao

Feifei Cheng

Kevin Joseph Doran

Konika Ganguly

Ajay Balankutty

Pascal A Meier

Jeffrey Lee

Arghya Sain

Jihwan Kim

Md Mohiuddin Mazumder

Michael E Ryan

Anupriya Sriramulu

Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

Ground via clustering for crosstalk mitigation

A microelectronic socket structure and a method of forming the same. The socket structure comprises: a socket structure housing defining a cavity therein; and an interconnection structure including: a contact element disposed at least in part within the cavity, and configured to be electrically coupled to a corresponding microelectronic package, the contact element corresponding to one of a signal contact element or a ground contact element; and a conductive structure disposed at least in part within the cavity, electrically coupled to the contact element, and having an outer contour that is non-conformal with respect to an outer contour of the contact element.

Heterogenous socket contact for electrical and mechanical performance scaling in a microelectronic package

Glass substrates having signal shielding for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a core layer defining a channel and a through glass via (TGV). The channel at least partially surrounding the TGV. A signal transmission line is provided in the opening and extending through the core layer. An electrically conductive material positioned in the channel. The conductive material to provide electromagnetic shielding to the transmission line.

Glass substrates having signal shielding for use with semiconductor packages and related methods

Integrated circuit packages may be formed having at least one optical via extending from a first surface of a package substrate to an opposing second surface of the package substrate. The at least one optical via creates an optical link between the opposing surfaces of the package substrate that enables the fabrication of a dual-sided optical multiple chip package, wherein integrated circuit devices can be attached to both surfaces of the package substrate for increased package density.

Through-substrate optical vias

Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

Power delivery for embedded bridge die utilizing trench structures

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first trace embedded in a package substrate. In an embodiment, the first trace comprises a first region, where the first region has a first width, and a second region, where the second region has a second width that is smaller than the first width.

Package design scheme for enabling high-speed low-loss signaling and mitigation of manufacturing risk and cost

Generally discussed herein are systems, devices, and methods to reduce crosstalk interference. An interconnect structure can include a first metal layer, a second metal layer, a third metal layer, the first metal layer closer to the first and second dies than the second and third metal layers, the first metal layer including a ground plane within a footprint of a bump field of the interconnect structure and signal traces outside the footprint of the bump field.

Die interconnect structures having bump field and ground plane

Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure on a low density interconnect (LDI) printed circuit board (PCB) according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region within the conductive structure. Other embodiments are described and claimed.

Fine feature formation techniques for printed circuit boards

An apparatus is provided which comprises: a substrate, the substrate comprising crystalline material, a first set of one or more contacts on a first substrate surface, a second set of one or more contacts on a second substrate surface, the second substrate surface opposite the first substrate surface, a first via through the substrate coupled with a first one of the first set of contacts and with a first one of the second set of contacts; a second via through the substrate coupled with a second one of the first set of contacts and with a second one of the second set of contacts, a trench in the substrate from the first substrate surface toward the second substrate surface, wherein the trench is apart from, and between, the first via and the second via, and dielectric material filling the trench. Other embodiments are also disclosed and claimed.

Dielectric-filled trench isolation of vias

Structures are described that include multi-layered adhesion promotion films over a conductive structure in a microelectronic package. The multi-layered aspect provides adhesion to surrounding dielectric material without a roughened surface of the conductive structure. Furthermore, the multi-layered aspect allows for materials with different dielectric constants to be used, the average of which can provide a closer match to the dielectric constant of the surrounding dielectric material. According to an embodiment, a first dielectric layer that includes at least one nitride material can provide good adhesion with the underlying conductive structure, while one or more subsequent dielectric layers that include at least one oxide material can provide different dielectric constant values (e.g., typically lower) compared to the first dielectric layer to bring the overall dielectric constant closer to that of a surrounding dielectric material. The first and second layers may be discrete layers or a single continuous layer with grading.

Multi-layered adhesion promotion films

Embodiments include a transmission line-land grid array (TL-LGA) socket assembly, a TL-LGA socket, and a package substrate. The TL-LGA socket assembly includes a TL-LGA socket having an interconnect in a housing body, the interconnect includes a vertical portion and a horizontal portion. The housing body has a top surface and a bottom surface, where the top surface is a conductive layer. The TL-LGA socket assembly also includes a package substrate having a base layer having a signal pad and a ground strip. The base layer is above the conductive layer of the housing body of the TL-LGA socket. The ground strip is above the horizontal portion of the interconnect and adjacent to the signal pad. The horizontal portion is coupled to the signal pad on the base layer. The package substrate may have a pad with a reduced pad area.

Selective ground flood around reduced land pad on package base layer to enable high speed land grid array (LGA) socket

Growing community of inventors

Chandler, AZ, United States of America

Kemal Aygun