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Daedalus Prime LLC

Kelin J Kuhn

Seiyon Kim

Rafael Rios

Stephen M Cea

Annalisa Cappellani

Tahir Ghani

Anand S Murthy

Willy Rachmady

Martin D Giles

Glenn A Glass

Mark Armstrong

Jack T Kavalieros

Roza Kotlyar

Abhijit Jayant Pethe

Ian A Young

Titash Rakshit

Peter Chang

Daniel Bourne Aubertine

Anurag Chaudhry

Sasikanth Manipatruni

Van H Le

Seung Hoon Sung

Uygar E Avci

Gilbert W Dewey

Benjamin Chu-Kung

Harold W Kennel

Markus Kuhn

Harry Gomez

Thomas D Linton, Jr

Debendra Mallik

Kevin Lai Lin

John C Johnson

Daniel A Simon

Chytra Pawashe

Fahmida Ferdousi

Marko Radosavljevic

Mark T Bohr

Dmitri E Nikonov

Aaron D Lilak

Gerhard Schrom

Christopher J Jezewski

Edward Allyn Burton

Rajesh Kumar

Peter G Tolchinsky

Nadia M Rahhal-Orabi

Patrick H Keys

Paul A Packan

Nancy M Zelick

Sunit Tyagi

Kaizad Rumy Mistry

Raseong Kim

Ian R Post

Scott E Thompson

Chris Auth

Chul-Hyun Lim

Sivakumar Mudanai

Richard K Hose, Jr

Mayank Sahni

Gopinath Bhimarasetti

Justin R Weber

Curtis W Ward

Daniel Pantuso

Michael C Mayberry

Lei Jiang

Patrick Theofanis

Jorge A Munoz

Edwin B Ramayya

Aura Cecilia Davila Latorre

Jr Thomas D Linton

A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.

Nanowire transistor fabrication with hardmask layers

A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Integration methods to fabricate internal spacers for nanowire devices

Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

Silicon and silicon germanium nanowire structures

Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

Nanowire structures having non-discrete source and drain regions

Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.

Method of fabricating CMOS FinFETs by selectively etching a strained SiGe layer

Method of fabricating a semiconductor device with strained SiGe fins and a Si cladding layer

Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.

Non-planar semiconductor device having hybrid geometry-based active region

Embodiments of the present disclosure describe techniques and configurations for integrated thermoelectric cooling. In one embodiment, a cooling assembly includes a semiconductor substrate, first circuitry disposed on the semiconductor substrate and configured to generate heat when in operation and second circuitry disposed on the semiconductor substrate and configured to remove the heat by thermoelectric cooling. Other embodiments may be described and/or claimed.

Integrated thermoelectric cooling

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Aloha, OR, United States of America

Kelin J Kuhn