Chinese Academy of Sciences

Other

Keke Zhang

Haizhou Yin

Huilong Zhu

Ming Liu

Qi Liu

Hangbing Lv

Shibing Long

Yunfei Liu

Haitao Sun

Kangwei Zhang

Writam Banerjee

A nonvolatile resistive switching memory, comprising an inert metal electrode, a resistive switching functional layer, and an easily oxidizable metal electrode, and characterized in that: a graphene barrier layer is inserted between the inert metal electrode and the resistive switching functional layer, which is capable of preventing the easily oxidizable metal ions from migrating into the inert metal electrode through the resistive switching functional layer under the action of electric field during the programming of the device. The manufacturing method therefore comprises adding a monolayer or multilayer graphene thin film between the inert electrode and the solid-state electrolyte resistive switching functional layer which services as a metal ion barrier layer to stop electrically-conductive metal filaments formed in the resistive switching layer from diffusing into the inert electrode layer during a RRAM device programming process, eliminating erroneous programming phenomenon occurring during the erasing process, improving device reliability.

Nonvolatile resistive switching memory device and manufacturing method thereof

A method of fabricating an asymmetric FinFET is provided in the invention, comprising: a. providing a substrate (); b. forming a fin () on the substrate (), wherein the width of the fin () is defined as a second channel thickness; c. forming a shallow trench isolation; d. forming a sacrificial gate stack on the top surface and sidewalls of the channel which is in the middle of the fin, and forming source/drain regions in both ends of the fin; e. depositing an interlayer dielectric layer to cover the sacrificial gate stack and the source/drain regions, planarizing the interlayer dielectric layer to expose sacrificial gate stack; f. removing the sacrificial gate stack to expose the channel; g. forming an etch-stop layer () on top of the channel; h. covering a photoresist film () on a portion of the semiconductor structure near the source region; i. thinning the channel which is not covered by the photoresist layer () from both direction vertical to the channel sidewalls until a first channel thickness obtained; j. removing the etch-stop layer (). Harmful short channel effects can be restrained and device performance can be enhanced.

Asymmetrical FinFET structure and method of manufacturing same

The present invention provides a method for manufacturing a semiconductor device, comprising: forming a contact sacrificial pattern on a substrate to cover source and drain regions and expose a gate region; forming an interlayer dielectric layer on the substrate to cover the contact sacrificial pattern and expose the gate region; forming a gate stack structure in the exposed gate region; removing the contact sacrificial pattern to form the source/drain contact trench; and forming a source/drain contact in the source/drain contact trench. By means of a contact sacrificial layer process, the method of manufacturing a semiconductor device according to the present invention effectively reduces the distance between the gate spacer and the contact region and increases the area of the contact region, thus effectively reducing the parasitic resistance of the device.

Method for manufacturing semiconductor devices

A method of manufacturing a FinFET device is provided, comprising: a. providing a substrate (); b. forming a fin () on the substrate; c. forming an shallow trench isolation structure () on the substrate; d. forming an sacrificial gate stack on the isolation structure, wherein the sacrificial gate stack intersects the fin; e. forming source/drain doping regions by ion implantation into the fin; f. depositing an interlayer dielectric layer () on the substrate; g. removing the sacrificial gate stack to form a sacrificial gate vacancy; h. forming an doped region () under the sacrificial gate vacancy; i. etching the shallow trench isolation structure () under the sacrificial gate vacancy until the top surface of the shallow trench isolation structure () levels with the bottom surface of the source/drain doping regions; j. forming a new gate stack in the sacrificial gate vacancy. Some advantages of the current invention may be, harmful effects produced in the source/drain regions by the triangle fin structure are eliminated, the device performance is improved, and the complexity of the process is reduce.

Method for manufacturing finFET

A method for manufacturing a semiconductor device is disclosed. The method comprises: forming a T-shape dummy gate structure on the substrate; removing the T-shape dummy gate structure and retaining a T-shape gate trench; forming a T-shape metal gate structure by filling a metal layer in the T-shape gate trench. According to the semiconductor device manufacturing method disclosed in the present application, the overhang phenomenon and the formation of voids are avoided in the subsequent metal gate filling process by forming a T-shape dummy gate and a T-shape gate trench, and the device performance is improved.

Semiconductor device and method for manufacturing the same

The present invention discloses a method for manufacturing a semiconductor device, comprising the steps of: forming a dummy gate stack structure on a substrate, wherein the dummy gate stack structure contains carbon-based materials; forming source/drain region in the substrate on both sides of the dummy gate stack structure; performing etching to remove the dummy gate stack structure until the substrate is exposed, resulting in a gate trench; and forming a gate stack structure in the gate trench. In accordance with the method for manufacturing a semiconductor device of the present invention, the dummy gate made of carbon-based materials is used to substitute the dummy gate made of silicon-based materials, then no oxide liner and/or etch blocking layer needs be added while the dummy gate is removed by etching in the gate last process, thus the reliability of device is ensured while the process is simplified and the cost is reduced.

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Beijing, China

Keke Zhang