International Business Machines Corporation

Infineon Technologies Ag

Keith Raymond Milkove

David V Horak

Steven J Holmes

Toshiharu Furukawa

Mark Charles Hakey

Charles Thomas Black

David James Frank

Kathryn Wilder Guarini

William Hsioh-Lien Ma

Michael C Gaidis

Rajiv M Ranade

Young Hoon Lee

Ihar Kasko

George Stojakovic

Russell D Allen

John William Stiebritz, Jr

Joachim Neutzel

Kim Poong Mee Lee, Legal Representative

A device and method for improving adhesion for thin film layers includes applying a diblock copolymer on a surface where adhesion to subsequent layers is needed and curing the diblock copolymer. Pores are formed in the diblock copolymer by treating the diblock copolymer with a solvent. The surface is etched through the pores of the diblock copolymer to form adhesion promoting features. The diblock copolymer is removed, and a layer is deposited on the surface wherein the adhesion promoting features are employed to promote adhesion between the layer and the surface.

Device and method for improving interface adhesion in thin film structures

A method of fabricating a magnetic tunnel junction (MTJ) device is provided. A patterned hard mask is oxidized to form a surface oxide thereon. An MTJ stack is etched in alignment with the patterned hard mask after the oxidizing of the patterned hard mask. Preferably, the MTJ stack etch recipe includes chlorine and oxygen. Etch selectivity between the hard mask and the MTJ stack is improved.

Fabrication process for a magnetic tunnel junction device

Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode pattern, depositing a dielectric layer upon said electrode pattern that substantially conforms to said topographic features, and depositing a second solid-state electrode pattern upon said dielectric layer and sufficiently insulated from said first solid-state electrode pattern so as to create a capacitance with said first solid-state electrode pattern.

Semiconductor with nanoscale features

Method for increasing the capacitance of a semiconductor capacitors

A method for etching silicon is described incorporating first and second steps of reactive ion etching through a patterned oxide layer in respective atmospheres of HBr, Cl.sub.2 and O.sub.2 and then HBr and O.sub.2 in situ by terminating the first etching step and removing substantially all Cl.sub.2 before continuing with the second step of etching. The invention overcomes the problem of uneven etching of n+ and p+ silicon gates for CMOS transistor logic during the step of simultaneously etching silicon to form sub 0.25 micron gate lengths and vertical sidewalls while stopping on the gate oxide.

Silicon etching method

Growing community of inventors

Beacon, NY, United States of America

Keith Raymond Milkove