Adeia Semiconductor Bonding Technologies Inc.

Keith L Barrie

Grant Villavicencio

Jeffrey S Leal

Suzette Keefe Pangrle

Reynaldo Co

Scott P McGrath

Elmer M Del Rosario

John R Bray

DeAnn Eileen Melcher

De Ann Eileen Melcher

Suzette K Pangrie

Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.

Electrical connector between die pad and z-interconnect for stacked die assemblies

A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to 'bleed' laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CFplasma treatment.

Semiconductor die having fine pitch electrical interconnects

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Capitola, CA, United States of America

Keith L Barrie