International Business Machines Corporation

Globalfoundries Inc.

Other

Freescale Semiconductor,inc.

Samsung Electronics Co., Ltd.

Infineon Technologies Ag

Advanced Micro Devices Corporation

Stmicroelectronics Gmbh

Globalfoundries U.S. 2 LLC

Infineon Technologies North America Corp.

Keith Kwong Hon Wong

Chih-Chao Yang

Dechao Guo

Shu-Jen Han

Lawrence Alfred Clevenger

Haining S Yang

Jun Yuan

Kangguo Cheng

Carl John Radens

Timothy Joseph Dalton

Yun-Yu Wang

Michael Patrick Chudzik

Unoh Kwon

Bruce Bennett Doris

Louis L Hsu

Zhengwen O Li

Baozhen Li

Junli Wang

Cyril Cabral, Jr

Fei Liu

Wilfried Haensch

Siddarth A Krishnan

Terence Lawrence Kane

Ruqiang Bao

Vijay Narayanan

Louis Lu-Chen Hsu

Eduard Albert Cartier

Thomas M Shaw

Huiming Bu

Michael C Gaidis

Chengwen Pei

Andrew Herbert Simon

Thomas W Dyer

Vamsi Krishna Paruchuri

Rajarao Jammy

Naim Moumen

Takashi Ando

Daniel C Edelstein

Christian Lavoie

Richard Stephan Wise

Brian Joseph Greene

Pranita Kulkarni

Louis C Hsu

Xinhui Wang

Vidhya Ramachandran

Nicolas L Breil

Daniel J Jaeger

Jack Allan Mandelman

Oleg Gluschenkov

Yun Yu Wang

Ramachandra Divakaruni

Mukta G Farooq

Praneet Adusumilli

Xin Ru Wang

Matthew Earl Colburn

Qing Cao

Supratik Guha

Ravikumar Ramachandran

Renee Tong Mo

Barry P Linder

Roger Allen Booth, Jr

Matthew Warren Copel

Philip Joseph Oldiges

Rishikesh Krishnan

Zhijian Yang

Xian Jay Ning

Alexander Reznicek

Edward J Nowak

Huilong Zhu

Veeraraghavan S Basker

Theodorus E Standaert

William R Tonti

Kevin K Chan

Shom Ponoth

Michael A Guillorn

Ying Di Zhang

Reinaldo Ariel Vega

Leland Chang

Zhen Zhang

Martin Michael Frank

Damon B Farmer

Ahmet Serkan Ozcan

Qiqing Christine Ouyang

Emre Alptekin

Li-Kong Wang

David Lee Rath

Richard Anthony Conti

Anna Wanda Topol

John Christopher Arnold

Michael P Belyansky

Kathryn Turner Schonenberg

William K Henson

Leathen Shi

Michael F Lofaro

Zhibin Ren

Nivo Rovedo

Joseph Francis Shepard, Jr

Deok-Kee Kim

Sunfei Fang

Hongwen Yan

An electrical fuse device is disclosed. A circuit apparatus can include the fuse device, a first circuit element and a second circuit element. The fuse includes a first contact that has a first electromigration resistance, a second contact that has a second electromigration resistance and a metal line, which is coupled to the first contact and to the second contact, that has a third electromigration resistance that is lower than the second electromigration resistance. The first circuit element is coupled to the first contact and the second circuit element coupled to the second contact. The fuse is configured to conduct a programming current from the first contact to the second contact through the metal line. Further, the programming current causes the metal line to electromigrate away from the second contact to electrically isolate the second circuit element from the first circuit element.

Electrical fuse with metal line migration

A cobalt contact includes a dual silicide barrier layer. The barrier layer, which may be formed in situ, includes silicides of titanium and cobalt, and provides an effective adhesion layer between the cobalt contact and a conductive device region such as the source/drain junction of a semiconductor device, eliminating void formation during a metal anneal.

Mechanically stable cobalt contacts

Aspects of the present disclosure include a method for forming a contact on a semiconductor device, the semiconductor device including a conductive region disposed over a substrate, the method comprising: depositing a dielectric material on the substrate; forming an opening in the dielectric material to expose the conductive region; forming a barrier layer on a lower surface and sidewalls of the opening in the dielectric material, the barrier layer terminating below an upper surface of the dielectric material and surrounding a lower portion of the opening; depositing cobalt in the lower portion of the opening, the cobalt terminating at an upper surface of the barrier layer; depositing tungsten to fill the opening to at least the upper surface of the dielectric material; and planarizing the upper surface of the dielectric material with the tungsten in the opening.

Method to form interconnect structure with tungsten fill

The present disclosure generally relates to semiconductor structures and, more particularly, to interconnect structures and methods of manufacture. The structure includes a metallization feature comprising a fill material and formed within a dielectric layer; at least one cap covering the fill material of the metallization feature, the at least one cap is comprised of a material different than the fill material of the metallization feature; and an interconnect structure in electrical contact with the metallization feature.

Interconnect structures

A method of forming a titanium nitride (TiN) diffusion barrier includes exposing a deposition surface to a first pulse of a titanium-containing precursor and to a first pulse of a nitrogen-rich plasma to form a first TiN layer with a first nitrogen concentration making a lower portion of the TiN diffusion barrier, the first nitrogen concentration of the first TiN layer is increased by the first pulse of the nitrogen-rich plasma reducing a reactivity of the lower portion of the TiN diffusion barrier to prevent fluorine diffusion. The first TiN layer is exposed to second pulses of the titanium-containing precursor and the nitrogen-rich plasma to form a second TiN layer with a second nitrogen concentration above the first TiN layer making an upper portion of the TiN diffusion barrier, the first pulse of the nitrogen-rich plasma has a substantially longer duration than the second pulse of the nitrogen-rich plasma.

Diffusion barrier layer formation

A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by implanting nitrogen into the structure.

Modified tungsten silicon

A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by changing the crystalline structure to a tetragonal tungsten silicon layer.

Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming an opening in a low-k dielectric layer; filling the opening with a high-k dielectric material; patterning the low-k dielectric layer outside of the opening and the high-k dielectric layer to form an interconnect opening within the low-k dielectric layer and a capacitor opening within the high-k dielectric layer; and filling the interconnect opening and the capacitor opening with a metal to form an interconnect in the low-k dielectric layer and a capacitor in the high-k dielectric layer.

Interconnect structure with capacitor element and related methods

A structure including a dual damascene feature in a dielectric layer, the dual damascene feature including a first via, a second via, and a trench, the first via, the second via being filled with a conductive material, a fuse line at the bottom of the trench on top of the first via and the second via, the fuse line including the conductive material; an insulating layer on top of the fuse line and along a sidewall of the trench, and a fill material on top of the insulating layer and substantially filling the trench.

Electronic fuse having an insulation layer

In one embodiment, a method of making a semiconductor device includes: forming a substrate; forming an nFET transistor and a pFET transistor on the substrate; wherein forming the nFET transistor comprises first depositing several first layers in and along the inner sidewalls of a trench on the substrate, then depositing a conductive metal comprising cobalt on the several first layers; wherein forming the pFET transistor comprises first depositing several second layers in and along the inner sidewalls of a trench on the substrate, then depositing a conductive metal comprising cobalt on the several second layers.

Low resistive electrode for an extendable high-k metal gate stack

Structures for a liner replacement in an interconnect structure and methods for forming a liner replacement in an interconnect structure. A metallization level is formed that includes a conductive feature. A dielectric layer is formed on the metallization level. The dielectric layer includes an opening that extends vertically through the dielectric layer to the conductive feature. An adhesion layer is formed on area of the conductive feature exposed at a base of the opening. The adhesion layer has a thickness equal to a monolayer or a fraction of a monolayer. Another layer (e.g., barrier layer) of a different composition (e.g., TiN) may be deposited on the adhesion layer before the opening is filled with metal deposited by chemical vapor deposition.

Liner replacements for interconnect openings

Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different threshold voltages are obtained by selectively incorporating metal layers with different work functions in different gate stack portions.

Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs

Growing community of inventors

Wappingers Falls, NY, United States of America

Keith Kwong Hon Wong