Kabushiki Kaisha Toshiba

Keishi Sakanushi

Chikaaki Kodama

Yoko Yokoyama

According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a memory cell array including a plurality of stacked memory cells, a plurality of first wirings electrically connected to the plurality of memory cells, a plurality of first contacts electrically connected to part of the plurality of first wirings and arranged in a first direction parallel to the semiconductor substrate, a plurality of second contacts electrically connected to part of the plurality of first wirings and arranged in the first direction alternately with the first contacts, a plurality of third contacts electrically connected to the first contacts and displaced from the first contacts in the first direction, and a plurality of fourth contacts electrically connected to the second contacts and displaced from the second contacts in a second direction perpendicular to the first direction.

Non-volatile memory device having 3D memory cell array with improved wordline and contact layout

According to one embodiment, a method is disclosed for designing an integrated circuit by a computer including an input unit, a memory unit, a calculating unit, and an output unit. The method can include storing a design model in the memory unit. The design model has parameters of physical quantities of active elements, passive elements, and an interconnection pattern included in the integrated circuit. The design model has an algorithm generating a circuit layout from values of the parameters. The method can include inputting the values of the parameters based on a first design specification of the integrated circuit by the input unit, generating a first circuit layout of the active elements, the passive elements, and the interconnection pattern by the calculating unit using the design model from the values of the parameters received by the input unit, and outputting the first circuit layout by the output unit.

Method and apparatus for generating circuit layout using design model and specification

In a design layout correcting method of an embodiment, a design layout of a circuit pattern is divided to a first mask pattern and a second mask pattern. The mask pattern of the pattern defect area of the first or second mask pattern is set as the correcting target pattern. A correcting target region and a verifying region are set within the first or second mask pattern. The correcting target pattern is corrected within the correcting target region, and the first and second mask patterns are verified within the verifying region.

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Kanagawa-ken, Japan

Keishi Sakanushi