Toshiba Memory Corporation

Keiko Kaneda

Tomoko Fujiwara

Takao Sueyama

Michiko Tsumura

Michiko Ego

A testing apparatus according to an embodiment includes a chamber, a probe card including probes exposed in the chamber, a stage supporting a test target object in the chamber, a moving mechanism to move the stage between a testing position where the test target object is in contact with the probes and a cleaning position where the test target object is arranged away from the probes in a horizontal direction, and an air tube introducing first dry air into the chamber through the probe card when the stage is placed at the cleaning position.

Testing apparatus

A semiconductor memory device includes an n-type source/drain formed in a surface region of a p-type active region, and a gate. The semiconductor memory device also includes a withstand voltage improvement layer provided with a preset distance maintained from at least one end of the source/drain. N-type impurities are diffused in the withstand voltage improvement layer, and a withstand voltage improvement voltage is applied to the withstand voltage improvement layer to expand a depletion layer to reach the source/drain, so that the maximum withstand voltage value of a transistor is increased.

Semiconductor device

A probe card includes a probe; and a probe card substrate which includes a first member and a second member, the first member having a first surface provided with the probe and the second member having a second surface surrounding the first surface, wherein a direction of the first surface is different from a direction of the second surface.

Growing community of inventors

Chiba, Japan

Keiko Kaneda