Sanyo Electric Co., Ltd.

Other

Semiconductor Components Industries, LLC

Sanyo Semiconductor Co., Ltd.

Sanyo Semiconductor Manufacturing Co., Ltd.

On Semiconductor Trading, Ltd.

Keiji Mita

Kentaro Ooka

Yasuhiro Tamada

Masao Takahashi

Takao Arai

Takao Maruyama

Osamu Shiroma

A semiconductor integrated circuit is reduced in size by suppressing lateral extension of an isolation region when impurities are thermally diffused in a semiconductor substrate to form the isolation region. Boron ions (B+) are implanted into an epitaxial layer through a third opening Kto form a P-type impurity region, using a third photoresist as a mask. Then a fourth photoresist is formed on a silicon oxide film to have fourth openings K(phosphorus ion implantation regions) that partially overlap the P-type impurity region. Phosphorus ions (P+) are implanted into the surface of the epitaxial layer in etched-off regions using the fourth photoresist as a mask to form N-type impurity regions that are adjacent the P-type impurity region. After that, a P-type upper isolation region is formed in the epitaxial layer by thermal diffusion so that the upper isolation region and a lower isolation region are combined together to make an isolation region.

Semiconductor device and manufacturing method thereof

In a semiconductor device including a protection diode for preventing electrostatic breakdown employing a low capacitance protection diode, an occupation area of a Zener diode as a voltage limiting element is not needed on a front surface of a semiconductor substrate. A P+ type embedded diffusion layer is formed in a P+ type semiconductor substrate. This is then covered by a non-doped first epitaxial layer. A high resistivity N type second epitaxial layer is then formed on the first epitaxial layer. The second epitaxial layer is divided by a P+ isolation layer into a first protection diode forming region and a second protection diode forming region. An N+ type embedded layer extending from the front surface of the first epitaxial layer of the first protection diode forming region to the first epitaxial layer and the second epitaxial layer, and so on are then formed. A Zener diode is formed by a P+ type upward diffusion layer extending from the P+ type embedded diffusion layer and the N+ type embedded layer.

Semiconductor device and method of manufacturing the same

A serially-connected diode pair made of diodes having a high withstand voltage and a low on-resistance is formed based on a high withstand voltage vertical PNP bipolar transistor process technology. Two of the diode pairs are connected in parallel to form a bridge so that there is formed a high-efficiency full-wave rectifier circuit that is free from a leakage current due to a parasitic transistor. The serially-connected diode pair is formed by connecting a diode composed of a P type semiconductor substrate, that makes an anode, and an N type buried layer, that makes a cathode, and a diode composed of a P+ type conductive layer, that makes an anode, and an N type epitaxial layer, that makes a cathode, in series with an electrode AC. An N+ type buried layer and an N+ type conductive layer are formed to prevent an electric potential at the N+ type buried layer from becoming lower than an electric potential at a P+ type buried layer even when a large positive voltage is applied to the electrode AC, so as to prevent a parasitic PNP transistor composed of the P+ type buried layer, the N+ type buried layer and the P type semiconductor substrate, that make an emitter, a base and a collector, respectively, from turning on.

Semiconductor device

A conventional semiconductor device has a problem that, when a vertical PNP transistor as a power semiconductor element is used in a saturation region, a leakage current into a substrate is generated. In a semiconductor device of the present invention, two P type diffusion layers as a collector region are formed around an N type diffusion layer as a base region. One of the P type diffusion layers is formed to have a lower impurity concentration and a narrower diffusion width than the other P type diffusion layer. In this structure, when a vertical PNP transistor is turned on, a region where the former P type diffusion layer is formed mainly serves as a parasite current path. Thus, a parasitic transistor constituted of a substrate, an N type buried layer and a P type buried layer is prevented from turning on, and a leakage current into the substrate is prevented.

A conventional semiconductor device, for example, a lateral PNP transistor has a problem that it is difficult to obtain a desired current-amplification factor while maintaining a breakdown voltage characteristic without increasing the device size. In a semiconductor device, that is a lateral PNP transistor, according to the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. The epitaxial layer is used as a base region. Moreover, molybdenum (Mo) is diffused in the substrate and the epitaxial layer. With this structure, the base current is adjusted, and thereby a desired current-amplification factor (hFE) of the lateral PNP transistor is achieved.

A semiconductor integrated circuit is reduced in size by suppressing lateral extension of an impurity region when impurities in the impurity region are thermally diffused in a semiconductor substrate. A second photoresist is formed on an insulation film. The second photoresist is formed to have second openings Kon both sides of a P-type impurity region so that the second openings Kpartially overlap the P-type impurity region. The insulation film is etched off together with an underlying surface of the semiconductor substrate using the second photoresist as a mask so as to remove the P-type impurity region partially. Then, phosphorus ions (P+) are implanted into the surface of the semiconductor substrate in the etched-off regions using the second photoresist as a mask to form N-type impurity regions that are adjacent the P-type impurity region. After removing the second photoresist, the impurities in the P-type impurity region and the impurities in the N-type impurity region are thermally diffused.

In a semiconductor device of the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. In the substrate and the epitaxial layer, an N type buried diffusion layer is formed on a P type buried diffusion layer. With this structure, an upward expansion of the P type buried diffusion layer is checked and a thickness of the epitaxial layer can be made small while maintaining the breakdown voltage characteristics of a power semiconductor element. Accordingly, a device size of a control semiconductor element can be reduced.

A photodiode built-in semiconductor device is provided that can prevent internal peripheral circuits from erroneously operating due to incident light entering slantingly, or not perpendicular to a top surface of the semiconductor chip. A semiconductor chip 20 includes a photodiode and its peripheral circuits. The region except for the photodiode is covered with a light shielding film 22 of aluminum metallization. An isolation region (P.sup.+) 23 is arranged at an outermost portion of the chip. A dummy island 24 is formed so as to surround the entire portion of the chip 20. An N.sup.+ -type low resistance region 25 is formed in the surface of the dummy island 24. The dummy photodiode is formed by applying a reverse bias potential across the PN junction defined between the isolation region 23 and the dummy island 24.

Photodiode built-in semiconductor device with dummy photodiode

An optical semiconductor includes a photo diode integrated with a transistor built on first and second epitaxial layers grown of intrinsic material on a lightly doped substrate. A separating area divides the optical semiconductor into first and second isolated islands. The separating area is made up of a three separating areas, united end to end to form a single separating area. The first separating area is diffused at least upward from an interface between the substrate and the first epitaxial area. The second separating area is diffused both downward and upward from an interface between the first and second epitaxial layers. The third separating area is diffused downward from the surface of the second epitaxial layer into the substrate. The photo diode is formed in the first island area, and the transistor is formed in the second island area. An offsetting layer in the surface of the substrate, at least below the first island, is counterdoped to expand the depth of the depletion layer of the photo diode. The separating area extends into the substrate to a depth exceeding to the depth of the counterdoped region.

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Gunma, Japan

Keiji Mita