Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Nuvoton Technology Corporation Japan

Keiichi Murayama

Akiyoshi Tamura

Kenichi Miyajima

Masanobu Nogome

Hirotaka Miyamoto

Katsuyoshi Jokyu

Kazutsune Miyanaga

Yoshitaka Kuroishi

Tsuyoshi Tanaka

Manabu Yanagihara

Yorito Ota

Masahiro Maeda

Katsuhiko Kawashima

Keisuke Kojima

Takeshi Fukui

Kazumi Tsutsumida

Toshiharu Tanbo

A semiconductor device manufacturing method includes: forming a first groove having depth H in a semiconductor layer; filling the first groove with an oxide film and forming a surface oxide film having thickness a on an upper surface of the semiconductor layer to equalize the oxide film and the surface oxide film in height; forming a second groove having depth h greater than thickness a, from an uppermost surface of a third oxide film; forming gate trenches deeper than depth H, in the semiconductor layer; depositing polysilicon until at least the gate trenches and the second groove are filled with polysilicon; forming a peripheral element by injecting an impurity into polysilicon deposited in the second groove; and making a thickness of the peripheral element equal to depth h by concurrently removing polysilicon deposited in the gate trenches and polysilicon deposited in the second groove until they become equal in height.

Manufacturing method and semiconductor device

A semiconductor device and manufacturing method satisfies both of the trade-off characteristic advantages of the HBT and the HFET. The semiconductor device is an HBT and HFET integrated circuit. The HBT includes a sub-collector layer, a GaAs collector layer, a GaAs base layer, and an InGaP emitter layer that are sequentially stacked. The sub-collector layer includes a GaAs external sub-collector region, and a GaAs internal sub-collector region disposed on the GaAs external sub-collector region. A mesa-shaped collector part and a collector electrode are separately formed on the GaAs external sub-collector region. The HFET includes a GaAs cap layer, a source electrode, and a drain electrode. The GaAs cap layer includes a portion of the GaAs external sub-collector region. The source electrode and the drain electrode are formed on the GaAs cap layer.

Semiconductor device

The object of the present invention is to provide a semiconductor device and the manufacturing method thereof which are capable of preventing decrease in the collector breakdown voltage and reducing the collector resistance. The semiconductor device according to the present invention includes: a HBT formed on a first region of a semiconductor substrate; and an HFET formed on a second region of the semiconductor substrate, wherein the HBT includes: an emitter layer of a first conductivity; a base layer of a second conductivity that has a band gap smaller than that of the emitter layer; a collector layer of the first conductivity or a non-doped collector layer; and a sub-collector layer of the first conductivity which are formed sequentially on the first region, and the HFET includes an electron donor layer including a part of the emitter layer, and a channel layer formed under the electron donor layer.

Semiconductor device having a hetero-junction bipolar transistor and manufacturing method thereof

The object of the present invention is to provide a heterojunction bipolar transistor with high breakdown tolerance which can be manufactured at a high reproducibility and a high yield, the heterojunction bipolar transistor includes: a sub-collector layer; a collector layer formed on the sub-collector layer; a base layer formed on the collector layer; and an emitter layer, which is formed on the base layer and is made of a semiconductor that has a larger bandgap than a semiconductor of the base layer, in which the collector layer includes: a first collector layer formed on the sub-collector layer; a second collector layer formed on the first collector layer; and a third collector layer formed between the second collector layer and the base layer, a semiconductor of the first collector layer differs from semiconductors of the third collector layer and the second collector layer, and an impurity concentration of the second collector layer is lower than an impurity concentration of the sub-collector layer and higher than an impurity concentration of the third collector layer.

Heterojunction bipolar transistor and manufacturing method thereof

A base mesa finger (an emitter ledge layer, a base layer, and a collector layer) is interposed between two collector fingers (collector electrodes), and on the base mesa finger, a base finger (a base electrode) and two emitter fingers (an emitter layerand an emitter electrode) on both sides of the base finger, are formed. The two emitter fingers are formed symmetric with respect to the base finger as a reference.

Bipolar transistor and power amplifier

On a high-concentration n-type first sub-collector layer, a high-concentration n-type second sub-collector layer made of a material having a small bandgap, an i-type or low-concentration n-type collector layer, a high-concentration p-type base layer, an n-type emitter layer made of a material having a large bandgap, a high-concentration n-type emitter cap layer, a high-concentration n-type emitter contact layer made of a material having a small bandgap are sequentially stacked. From the emitter contact layer, an interconnection also serving as an emitter electrode is extended. From the emitter layer or the base layer, an interconnection also serving as a base electrode is extended. From the second sub-collector layer, an interconnection also serving as a collector electrode is extended.

Heterojunction bipolar transistor and method for fabricating the same

The present invention aims at providing a heterojunction bipolar transistor having improved breakdown voltage on operation for high power output, and includes: a GaAs semiconductor substrate; an n-type GaAs sub-collector layer; an n-type GaAs collector layer; a p-type GaAs base layer; an emitter layer; an n-type GaAs emitter cap layer; and an n-type InGaAs emitter contact layerThe emitter layerhas a multilayer structure including an n-type or non-doped first emitter layerand an n-type second emitter layerwhich are laminated in sequence. The first emitter layeris made of a semiconductor material including Al, while the second emitter layeris made of InGa1-xP (0&#x3c;x&#x3c;1).

Heterojunction bipolar transistor having an emitter layer made of a semiconductor material including aluminum

A hetero-junction bipolar transistor that satisfies high resistance required to avoid a potential breakdown includes: an n-type sub-collector layerthat is made of GaAs; an n-type first collectorthat is made of a semiconductor material with a smaller avalanche coefficient than that of the sub-collectorand is formed on the sub-collector layer; a second collector layerthat is made of n-type or i-type GaAs with lower dopant concentration than that of the sub-collector layerand is formed on the first collector layer; a p-type base layerthat is made of GaAs and is formed on the second collector layer; and emitter layerthat is made of a semiconductor material with a larger band gap than that of the base layerand is formed on the base layer

Hetero-junction bipolar transistor and manufacturing method thereof

A heterojunction bipolar transistor comprises a collector layer, a base layer formed on the collector layer and an emitter layer formed on the base layer. The emitter layer includes a first semiconductor layer covering the entire top surface of the base layer and a second semiconductor layer formed on a predetermined part of the first semiconductor layer. An inactivated region is formed, by ion implantation, in a region of the collector layer located below the base layer except for a part thereof corresponding to the second semiconductor layer. The edge of the inactivated region is located away from the edge of the second semiconductor layer, and a region of the first semiconductor layer between the edge of the inactivated region and the edge of the second semiconductor layer is depleted.

Semiconductor element and method for fabricating the same

A semiconductor device is provided having an improved breakdown voltage on high power output, the semiconductor device comprising a n-type GaAs subcollector layer, a n-type GaAs intermediate collector layer formed between a collector layer and the subcollector layer, the n-type GaAs collector layer, a p-type GaAs base layer, a n-type InGaP second emitter layer, a n-type GaAs first emitter layer, and a n-type InGaAs emitter contact layer, and a concentration of impurities in the intermediate collector layer is higher than a concentration of impurities in the collector layer and is lower than a concentration of impurities in the subcollector layer.

A semiconductor device includes a substrate with a via hole. An electrode is formed on a surface of the substrate so that a portion of the electrode extends through the via hole. A photosensitive resin is formed over the surface so as to cover an aperture of the via hole.

Semiconductor device including a photosensitive resin covering at least a portion of a substrate having a via hole

The following layers are successively formed on a heavily-doped n-type first subcollector layer: a heavily-doped n-type second subcollector layer made of a material having a small band gap; an i-type or a lightly-doped n-type collector layer; a heavily-doped p-type base layer; an n-type emitter layer made of a material having a large band gap; a heavily-doped n-type emitter cap layer; and a heavily-doped n-type emitter contact layer made of a material having a small band gap. Alloying reaction layers are formed under an emitter electrode, a base electrode and a collector electrode.

A GaAs substrateis rotated, a photosensitive silicone resistis applied on a surface of the GaAs substrateon which an aperture of a holeto be a via hole, and an inside of the holeto be the via hole is filled in with the photosensitive silicone resistNext, the GaAs substrateis further rotated, changing the number of revolutions (rpm), and the photosensitive silicone resiston the GaAs substrate is flattened. Next, a reverse side of the GaAs substrate is grinded, the holeto be the via hole penetrates the GaAs substratefrom the surface to the reverse side and the via holeis formed. Next, a reverse side electrodeis formed on the reverse side of the GaAs substrateNext, the GaAs sustrateis divided chip by chip and chips are laid on a substrate for assemblyvia an adhesive metal

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Toyama, Japan

Keiichi Murayama