Hitachi, Ltd.

Other

Hitachi Vlsi Engineering Corp.

Hitachi Microcomputer System, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Renesas Technology Corp.

Hitachi Ulsi Engineering Corp.

Keiichi Kurakazu

Yasushi Akao

Kouki Noguchi

Shumpei Kawasaki

Shiro Baba

Yugo Kashiwagi

Takanaga Yamazaki

Mitsuru Watabe

Toshimasa Kihara

Takashi Tsukamoto

Shigeki Masumura

Masahiro Kainaga

Kaoru Fukada

Eiji Sakakibara

Yoichi Asano

Katsuhiko Ishida

Yasuhiro Tawara

Shuya Fujita

Noriko Sawa

Hideaki Chaki

Tadahiko Sugawara

Kiyoshi Matsubara

Atsushi Hasegawa

Hiroshi Ohsuga

Yoshitaka Ito

Akio Hayakawa

Keisuke Toyama

Hiroyuki Kida

Tan Watanabe

Hideo Maejima

Ikuya Kawasaki

Satoshi Masuda

Yoshikazu Aoto

Susumu Kaneko

Shinji Kawashima

Yoshiaki Naruse

Tohru Nojiri

Thoru Nojiri

Toshio Tanaka

Takashi Maruyama

Haruo Keida

Takeshi Kataoka

Yosuke Murayama

Mitsuhiro Miyazaki

Tatsuo Nakai

Masayasu Ohizumi

Kazuyoshi Kikuta

Makoto Takano

Yasuhiko Hoshi

Masaharu Ando

Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Microcomputer and dividing circuit

A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Single-chip microcomputer with integral clock generating unit providing clock signals to CPU, internal circuit modules and synchronously controlling external dynamic memory

Single-chip microcomputer with hierarchical internal bus structure having data and address signal lines coupling CPU with other processing elements

Processing system with microcomputers each operable in master and slave modes using configurable bus access control terminals and bus use priority signals

A data processor including a central processing unit and a plurality of direct map cache memories ( ) has a plurality of area designating circuits ( ) for variably designating location and size of address area in the memory space managed the central processing unit and partially overlaps the address area designated by a plurality of area designating circuits. Thereby, the overlapped area (Eco) has a function as the 2-way set associative cache memory in combination with a plurality of cache memories. For the non-overlapping area, respective cache memory functions as the direct map cache memory. It is previously judged to attain the necessary data processing capability by arranging which processing routine to which address area and then executing such routine with what processing speed. Thereby, when cache object area is assigned to a plurality of cache memory, a plurality of cache memories are combined as a set associative cache for operation to the task which particularly requires high speed operation or to the data. As a result, the system can be optimized by improving the cache hit rate of the necessary area.

Data processor and data processing system

A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Microcomputer system with at least first and second microcomputers each operable in master and slave modes with configurable bus access control terminals and bus use priority controller

Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation

A microcomputer CMU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word

Single-chip microcomputer synchronously controlling external synchronous memory responsive to memory clock signal and clock enable signal

Single-chip microcomputer operable in master and slave modes and having configurable bus control terminals

A branch instruction format has different respective field lengths for conditional branch instructions and unconditional branch instructions. A conditional branch instruction has a first bit length and a first area for a displacement designating an address to be jumped, wherein the first area has a second bit length that is smaller than the first bit length. An unconditional branch instruction also has the first bit length, and a second area for a displacement designating an address to be jumped, wherein the second area has a third bit length that is different from the first and second bit lengths.

Branch instruction having different field lengths for unconditional and conditional displacements

Microcomputer having variable bit width area for displacement

Central processing unit having instruction queue of 32-bit length

Microcomputer having variable bit width area for displacement and

Growing community of inventors

Tokorozawa, Japan

Keiichi Kurakazu