Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Saint-gobain Placo

Verisilicon Microelectronics (shanghai) Co., Ltd.

Verisilicon Microelectronics (nanjing) Co., Ltd.

Verisilicon Holdings Company Ltd.

Verisilicon Microelectronics (chengdu) Co., Ltd.

Honeywell (china) Co., Ltd.

Chinese Academy of Sciences

Guangzhou University

Shanghai Fourier Intelligence Co., Ltd

Hanyi Bio-technology Company Ltd.

Ke Zhang

Liang Li

Ming Hsi Wang

Minna Li

Jiahui Yuan

Hao Song

Huifen Li

Xiaotong Gao

Xiang Yang

Muhammad Masuduzzaman

Tingting Yu

Huiming Zhang

Ming Wang

Mankit Lo

Chin-Yi Chen

Xiaojia Jia

Li Liang

Xin Tan

Hongda Li

Zhonghao Cui

Shuxi Lin

Linnan Chen

Weihao Chen

Yongkui Yu

Naihe Jing

Dongxiao Shao

Zhihao Yang

Jiajun Sun

Danping Xiao

Yanan Wu

Qian Jin

Tanran Chang

A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes coupled to bit lines. A control means successively applies each of a series of pulses of a program voltage to selected ones of the word lines while simultaneously applying one of a bit line program voltage and a bit line inhibit voltage to ones of the bit lines coupled to the memory holes containing groups of the memory cells connected to the selected ones of the plurality of word lines to program the groups of the memory cells with data. The control means maintains a voltage applied to ones of the plurality of bit lines as the bit line inhibit voltage in response to the ones of the plurality of bit lines remaining unselected when programming a next one of the groups of the memory cells.

Active current consumption save mode for non-volatile memory using fast programming

Provided are cross-linking method and apparatus, electronic device and storage medium. The method includes: modifying a register address in a first operation instruction of a library function after the register address in the first operation instruction hits a preset mapping table, wherein the mapping table includes a mapping relationship between a target register address of a main program and the register address of the library function, the target register address of the main program is increased to a first address bit number, the register address in the operation instruction of the library function has a second address bit number, the first address bit number is greater than the second address bit number, and the modified register address in the first operation instruction is the target register address of the corresponding main program in the mapping table; and migrating the modified first operation instruction into the main program.

Cross-linking method and apparatus, electronic device and storage medium

The memory device that includes a die with a CMOS wafer with programming and erasing circuitry. The die also includes a plurality of array wafers coupled with and in electrical communication with the CMOS wafer and having different programming and erasing efficiencies. Each of the array wafers includes memory blocks with memory cells. The control circuitry of the CMOS wafer is configured to output at least one of different initial programming voltages and unique erase voltages to the plurality of array wafers.

Array dependent voltage compensation in a memory device

A non-volatile memory system includes a control circuit connected to non-volatile memory cells. The control circuit is configured to concurrently program memory cells connected to different word lines that are in different sub-blocks of different blocks in different planes of a die.

Non-volatile memory with concurrent sub-block programming

A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes and configured to retain a threshold voltage. The memory holes are organized in rows grouped in strings and the strings comprise a plurality of blocks which comprise planes. A control means is configured to program the memory cells connected to one of the word lines and associated with one of the strings in each of the plurality of planes and acquire a smart verify programming voltage individually for each of the planes in a smart verify operation. The control means concurrently programs at least some of the memory cells connected to each of the word lines in each of the planes in a program operation using the smart verify programming voltage individually acquired for each of the planes in the smart verify operation.

Plane level dedicated starting program voltage to reduce program time for multi-plane concurrent program operation

Technology for open block boundary group programming of non-volatile memory such as NAND. The open block boundary group could potentially be read in response to a request from a host for the data stored in the group. In an aspect, the memory system will determine whether programming a group of memory cells in a selected block will result in an open block. If it will not result in an open block, then the memory system uses a first set of programming parameters to program the group. However, if it will result in an open block then the memory system uses a second set of programming parameters to program the boundary group. The programming parameters may include verify levels and/or a program voltage step size. The second set of programming parameters can tighten Vt distributions, which mitigates mis-reads if the boundary group is read.

Open block boundary group programming for non-volatile memory

The memory device includes a plurality of memory cells arranged in a plurality of blocks, which are arranged in at least one plane. A controller is in electrical communication with the plurality of memory cells. The controller is configured to define a multi-block group that includes at least two blocks to be erased. The controller is further configured to simultaneously apply at least one erase pulse to the multi-block group. The controller is further configured to individually and sequentially apply a verify pulse to the blocks. In response to all blocks passing verify, the controller is configured to complete the erase operation. In response to at least one of the blocks not passing verify, the controller is configured to individually and sequentially apply an erase pulse and then a verify pulse to the at least one block that did not pass verify.

Hybrid multi-block erase technique to improve erase speed in a memory device

A memory device including an array of memory cells arranged in a plurality of word lines is provided. A control circuitry is configured to program the memory cells of a selected word line to a plurality of leading data states in a plurality of programming loops that include programming and verify pulses. The control circuitry is also configured to count a total number of programming loops during programming of the selected word line. The control circuitry is also configured to program at least one memory cell of the selected word line to a last data state in at least one last data state programming loop. In response to both the total number of programming loops being less than a first predetermined threshold and the number of last data state programming loops being equal to a second predetermined threshold, the control circuitry automatically skips verify in a final programming loop.

Programming techniques to improve programming time and reduce programming errors

To remedy short term data retention issues, a non-volatile memory performs a multi-pass programming process to program data into a set of non-volatile memory cells and identifies non-volatile memory cells that experienced downward threshold voltage drift after a first pass of the multi-pass programming process and prior to a final pass of the multi-pass programming process. The final pass of the multi-pass programming process comprises programming non-volatile memory cells not identified to have experienced the downward threshold voltage drift to a set of final target threshold voltages and purposefully overprogramming non-volatile memory cells identified to have experienced the downward threshold voltage drift to threshold voltages greater than respective final target threshold voltages by one or more offsets.

Non-volatile memory with intentional overprogramming to improve short term data retention issue

The memory device includes a controller that is configured to program a plurality of memory cells of a selected word line in a plurality of programming loops and count the number of programming loops to complete programming. The controller is also configured to compare the number of programming loops to complete programming of the memory cells of the selected word line to at least one of a predetermined upper limit and a predetermined lower limit to determine if a plane containing the selected word line is at an elevated risk for read failure. In response to the controller making a determination that the plane containing the selected word line is at an elevated risk for read failure, the controller is configured to conduct a post write read operation at least one word line of the plurality of word lines.

Post-write read techniques to improve programming reliability in a memory device

A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in strings and are configured to retain a threshold voltage corresponding to data states. A control means is configured to apply verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above each of the program verify voltages associated with the data states targeted for each of the memory cells being programmed during verify loops of a program-verify operation. The control means slows the memory cells targeted for a selected one of the data states identified as being faster to program than other ones of the memory cells during one of verify loops associated with an earlier one of data states.

State look ahead quick pass write algorithm to tighten ongoing natural threshold voltage of upcoming states for program time reduction

To increase the speed of programming of a multi-plane non-volatile memory, it is proposed to accelerate the programming of the last one or more data states for one or more slow planes.

Non-volatile memory with enhanced program operation for last state on slow plane

An apparatus is provided that includes a memory die having a first memory cell, and a controller connected to the memory die. The controller is configured to apply a plurality of programming pulses to the first memory cell, apply a plurality of first verify pulses to the first memory cell, determine from the first verify pulses that the first memory cell has been programmed to a first programmed memory state, apply a single second verify pulse to the first memory cell after determining that the first memory cell has been programmed to the first programmed memory state, determine from the single second verify pulse that the first memory cell is no longer programmed to the first programmed memory state, and apply an additional programming pulse to the first memory cell.

Apparatus and methods for programming memory cells

A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes and configured to retain a threshold voltage. The memory holes are organized in rows grouped in strings. A control means is coupled to the word lines and the memory holes and programs the memory cells associated with a first one of the strings in a program operation and acquire a smart verify programming voltage in a smart verify operation including smart verify loops. The control means discards the smart verify programming voltage and determines another smart verify programming voltage in another smart verify operation on the memory cells associated with a second one of the strings in response to a quantity of the smart verify loops needed to complete programming of the memory cells associated with the first one of the strings being outside a predetermined threshold criteria.

Self-diagnostic smart verify algorithm in user mode to prevent unreliable acquired smart verify program voltage

Apparatuses and techniques are described for detecting and isolating defective blocks of memory cells in a multi-plane operation such as program or erase. In one aspect, a program operation begins in a multi-plane mode, for one block in each plane. If fewer than all blocks complete programming by the time a trigger number of program loops have been performed, one or more unpassed blocks are programmed further, one at a time, in a single plane mode. If the one or more unpassed blocks do not complete programming when a maximum allowable number of program loops have been performed, they are marked as bad blocks and disabled from further operations. In another aspect, when a trigger number of program loops have been performed, one or more unpassed blocks are subject to a word line leakage detection operation.

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Shanghai, China

Ke Zhang