Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Renesas Technology Corp.

Other

Hitachi Ulsi Engineering Corp.

Semiconductor Leading Edge Technologies, Inc.

Kazuyoshi Torii

Hideo Aoki

Isamu Asano

Tsuyoshi Tamaru

Yoshinao Kawasaki

Masakazu Sagawa

Nobuo Owada

Osamu Tsuchiya

Toru Kaga

Fumio Ootsuka

Hiromichi Enami

Mitsuaki Horiuchi

Jun Sugiura

Osamu Kasahara

Hidetsugu Ogishi

Makoto Ogasawara

Keisuke Funatsu

Masatoshi Tsuneoka

Takayoshi Kogano

Seiichirou Shirai

Atsushi Wakahara

Hiroyuki Akimori

Sinichi Suzuki

Nobuhiro Otsuka

Yoshihiro Ikeda

Tomotsugu Shimmyo

Tunehiko Tubone

Ken Tsugane

Hiroshi Miki

Yoshihisa Fujisaki

Keiko Kushida

Yasuhiro Shimamoto

Masahiro Moniwa

Masahiko Hiratani

Hiroshi Kawakami

Shinichiro Takatani

Takahiro Onai

Katsunori Obata

Shoji Shukuri

Digh Hisamoto

Toshiyuki Mine

Takeo Shiba

Hideyuki Matsuoka

Natsuki Yokoyama

Hiromasa Noda

Shinichiro Kimura

Shinichi Saito

Masahiko Ando

Ryuta Tsuchiya

Masatada Horiuchi

Kazunori Tsujimoto

Eiji Takeda

Tadashi Arai

Toshiyuki Yoshimura

Takaaki Kawahara

Riichirou Mitsuhashi

Atsushi Horiuchi

Yuuichi Matsui

An electrode substrate in which a lower electrode and an upper electrode are well positioned by way of an insulating film could not be formed by a printing method since positional displacement is caused. The cost was increased outstandingly when using photomasks for positioning. In the present invention, positional displacement does not occur even when using the printing method since the upper electrode and the lower electrode are positioned in self-alignment. Accordingly, a semiconductor device such as a flexible substrate using an organic semiconductor can be formed with low cost by using the printing method.

Method of manufacturing a semiconductor device having an organic thin film transistor

In a method for manufacturing an FET having a gate insulation film with an SiOequivalent thickness of 2 nm or more and capable of suppressing the leak current to 1/100 or less compared with existent SiOfilms, an SiOfilm of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiOfilm is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.

Semiconductor device and manufacturing method thereof

A method for manufacturing a semiconductor device includes forming a first insulating film on a substrate, forming a second insulating film on the first insulating film, and forming a gate electrode on the second insulating film. Forming the second insulating film includes supplying film-forming materials and adsorbing the film-forming materials on the first insulating film, purging the film-forming materials that have not been adsorbed, supplying oxidants to oxidize the adsorbed film-forming materials, and purging the oxidants that have not contributed to oxidization. Forming the second insulating film is repeated in cycles, continuously, and the purging time of the oxidants in an initial number of the cycles is longer than the purging time of the oxidants in cycles following the initial number of cycles.

Method for manufacturing semiconductor device

In a miniaturized field effect transistor, the roughness of the interface between a gate dielectric film and a gate electrode is controlled on an atomic scale. The thickness variation of the gate dielectric film is lowered, whereby a field effect transistor with high mobility is manufactured. An increase in the mobility in the field effect transistor can be achieved not only in the case of using a conventional SiOthermal oxide film as the gate dielectric film but also in the case of using a high dielectric material for the gate dielectric film.

Semiconductor device and manufacturing thereof

Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same

In a method for forming a semiconductor device, the major surface of a substrate is separated into a first element region for forming a first field-effect transistor and a second element region for forming a second field-effect transistor. A silicon nitride film is formed in each of the first and second element regions. Thereafter, the silicon nitride film formed in the second element region is removed, and the substrate is subjected to heat treatment in an ambient that contains nitrogen oxide. Thereby, the silicon nitride film in the first element region is oxidized to form an oxynitride film, and a silicon oxynitride film is formed in the second element region. Thereafter, a high-dielectric-constant film is formed on the silicon oxynitride films in each of the first and second element regions.

Semiconductor device and method for manufacturing semiconductor device

It is an object of the present invention to provide a fine memory cell structure preventing a reaction between an interlayer insulating film and a ferroelectric film and suitable for high integration. According to the invention, there is provided a structure in which a reaction barrier film is interposed between a ferroelectric film and an interlayer insulating film and side walls of a diffusion barrier film are not brought into direct contact with the ferroelectric film . Thereby, the reaction between the interlayer insulating film and the ferroelectric film can be restrained and exfoliation of the ferroelectric film can be prevented.

Memory structure with a ferroelectric capacitor

A semiconductor device includes a capacitor having a lower electrode ( ), a high-dielectric-constant or ferroelectric thin film ( ), and an upper electrode ( ) which are subsequently stacked. An impurity having an action of suppressing the catalytic activity of a metal or a conductive oxide constituting the electrode is added to the upper electrode ( ). The addition of the impurity is effective to prevent inconveniences such as a reduction in capacitance, an insulation failure, and the peeling of the electrode due to hydrogen heat-treatment performed after formation of the upper electrode ( ), and to improve the long-term reliability.

Semiconductor device and fabrication method thereof

In a method for manufacturing an FET having a gate insulation film with an SiO equivalent thickness of 2 nm or more and capable of suppressing the leak current to {fraction (1/100)} or less compared with existent SiO films, an SiO film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.

Semiconductor device having a replacement gate type field effect transistor and its manufacturing method

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A FIRST WIRING STRIP EXPOSED THROUGH A CONNECTING HOLE, A TRANSITION-METAL FILM IN THE CONNECTING HOLE AND AN ALUMINUM WIRING STRIP THEREOVER, AND A TRANSITION-METAL NITRIDE FILM BETWEEN THE ALUMINUM WIRING STRIP AND THE TRANSITION-METAL FILM

A diffusion preventive layer extending between the bottom surface of a lower electrode and an interconnection connecting the lower electrode to one of the diffusion layer of a switching transistor is self-aligned. As a result, side trench is produced since a hole pattern is formed by using a dummy film, and even if a contact plug of a memory section is misaligned with the diffusion preventive layer, the contact plug is out of direct contact with a dielectric film having a high permittivity. Hence, a highly reliable device can be obtained.

Ferroelectric capacitor with a self-aligned diffusion barrier

A semiconductor device having a bottom electrode, a ferroelectric film, and a top electrode formed on a semiconductor substrate, wherein the angle of each of the main cross sectional sides of the ferroelectric film relative to the main surface of the semiconductor substrate is less than 75 degrees. Forming the ferroelectric film into the trapezoid in cross section having such an angle provides a microscopic capacitor without electrical short-circuit between the top and bottom electrodes if the top electrode, the ferroelectric film, and the bottom electrode are etched with single photolithography process step. The novel technique implements a microscopic memory cell structure suitable for highly integrated memory devices.

Method of fabricating semiconductor device

Semiconductor device and method for manufacturing the same

A diffusion preventive layer extending between the bottom surface of a lower electrode and an interconnection connecting the lower electrode to one of the diffusion layers of a switching transistor is self-aligned. As a result, no side trench is produced since a hole pattern is formed by using a dummy film, and even if a contact plug of a memory section is misaligned with the diffusion preventive layer, the contact plug is out of direct contact with a dielectric film having a high permittivity. Hence, a highly reliable device can be obtained.

Growing community of inventors

Kodaira, Japan

Kazuyoshi Torii