Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Kazuya Nishihori

Yoshiaki Kitaura

Keita Masuda

Kyoichi Suguro

Kazuhide Abe

Tomonori Aoyama

Shuichi Komatsu

Kumi Okuwada

Masami Nagaoka

Yoshikazu Tanabe

Naotaka Uchitomi

Takahiro Nakagawa

Tadahiro Sasaki

Takao Noda

Atsushi Kameyama

Kenichi Tomita

Mayumi Morizuka

Mitsutoshi Nakamura

Yoshitomo Sagae

Hirotsugu Wakimoto

Masanori Ochi

Tomotoshi Inoue

Hitoshi Mikami

Kenji Hommyo

Kazuhiko Shibata

Tooru Suga

A semiconductor device includes an insulating layer, a semiconductor layer on the insulating layer, and a control electrode on the semiconductor layer. The semiconductor layer includes first and second semiconductor parts and a separation trench between the first and second semiconductor parts. The first and second semiconductor parts extending along the insulating film. The first semiconductor part includes first and second regions of a first conductivity type, and a fifth region of a second conductivity type between the first and second regions. The second semiconductor part includes third and fourth regions of the second conductivity type, and a sixth region of the second conductivity type between the third and fourth regions. The control electrode extends over the fifth and sixth regions. The semiconductor layer further including a seventh region of the second conductivity type at a bottom of the separation trench and electrically connecting the fifth and sixth regions.

Semiconductor device having semiconductor region at bottom of separation trench and connecting two semiconductor regions over which control electrode extends

A high frequency transistor includes a first semiconductor layer, a first insulating film and a control electrode. The first semiconductor layer on the first insulating film extends in a first direction along an upper surface of the first insulating film. The first semiconductor layer has a first layer thickness in a second direction perpendicular to the upper surface, and a first width in a third direction orthogonal to the first direction. The first width is greater than the first layer thickness. The control electrode covers upper and side surfaces of the first semiconductor layer. The first semiconductor layer includes a first region of a first conductivity type, second and third regions of a second conductivity type. The first to third regions are arranged in the first direction. The first region is provided between the second and third region. The control electrode covers the first region.

High frequency transistor

A radio frequency switch includes a switch circuit having switchable radio frequency (RF) signal pathways. Each switchable RF signal pathway comprises a plurality of n-type MOSFETs connected in series. A control circuit is configured to control a conduction state of the plurality of switchable RF signal pathways. Each n-type MOSFET includes a body region between a source region thereof and a drain region thereof. A gate electrode is on the body region. A silicon nitride film having a tensile internal stress covers the source layer, the drain layer, and the gate electrode.

Semiconductor switch

A semiconductor device according to an embodiment switches high-frequency signals and includes a semiconductor layer of a first conductivity type. A first layer of a second conductivity type is provided in the semiconductor layer. A second layer of the second conductivity type is provided in the semiconductor layer. A gate dielectric film is provided on the semiconductor layer, the first layer and the second layer. A gate electrode is provided on the gate dielectric film. The gate dielectric film includes a first portion and the semiconductor layer, and a second portion located at both side of the first portion-in a gate length direction of the gate electrode and being thicker than the first portion. At least a part of the second portion is located between the gate electrode and the first layer and between the gate electrode and the second layer.

Semiconductor device

According to an embodiment, a method for measuring an impurity concentration profile uses a wafer including a semiconductor layer. The method includes measuring an impurity concentration profile in a depth direction from each surface of a plurality of first portions, each of the first portions being included in any one of a plurality of first regions provided in the semiconductor layer. Each of the first regions has a different size and is surrounded by a second region including a second portion having a different structure from the first portion. The method includes determining a change between the impurity concentration profiles measured in the first regions.

Method for measuring impurity concentration profile, wafer used for same, and method for manufacturing semiconductor device using same

A heterojunction type compound semiconductor field effect transistor includes a channel layer, a first electron supply layer, an electric field strength reducing layer, a first contact layer, a recess stopper layer, and a second contact layer sequentially stacked on a compound semiconductor substrate. This transistor has a double recess structure. The first contact layer is composed of GaAs or InGaAs doped with n type impurities with a high electron mobility. The electric field strength reducing layer is composed of intrinsic InGaP.

Heterojunction type compound semiconductor field effect transistor and its manufacturing method

A MESFET of a GaAs semiconductor device having a p-pocket LDD structure is used for a high-frequency power amplifier of a mobile communication device, in order to decrease current consumption and to increase the continuous operating time of a battery. The high-frequency power amplifier is provided with a gate-bias adjusting feedback element between the drain and gate of the MESFET. Thus, even if there is a great difference between the filled and terminated potentials of the discharge voltage of the battery for supplying electric power to the amplifier, electric power can be supplied near the terminated potential for a long time, so that the mobile communication device can be continuously used for a long time.

High-frequency power amplifier and mobile communication device using same

A manufacturing method of compound semiconductor field effect transistor capable of enhancing a gate/drain withstand voltage includes a step of forming a channel layer by implanting ions into the surface of a semi-insulating compound semiconductor substrate and a step of performing a first thermal treatment for removing crystalline defects on the surface of the channel layer. This method also includes a step of forming a compound semiconductor epitaxial layer by use of an epitaxial method on a region covering the channel layer, a step of forming a gate electrode within a region on the epitaxial layer just above the channel layer and a step of forming a source region and a drain region in the substrate. A concentration of the impurity for forming the channel layer at an interface between the channel layer and the epitaxial layer is 45% or under of the highest concentration when forming the channel layer. A good interface between the channel layer and the epitaxial layer can be thereby obtained, and a transistor having the high-quality epitaxial layer can be also acquired.

Manufacturing method of compound semiconductor field effect transistor

An SiO.sub.2 film and a first wiring layer are arranged in this order on a GaAs substrate. A capacitor is formed on the first wiring layer. The capacitor includes a lower electrode which has a multi-layer structure consisting of a Ti layer, an Mo layer, and a Pt layer in this order from underside. The capacitor also includes a dielectric film made of strontium titanate. The capacitor further includes an upper electrode which has a multi-layer structure consisting of a WN.sub.x layer (120 nm) and a W layer (300 nm) in this order from underside. That surface of the upper electrode, which is in contact with the dielectric film, is defined by the tungsten nitride layer.

MMIC semiconductor device with WN.sub.x capacitor electrode

A semiconductor device in which an SiO.sub.2 film and a first wiring layer are arranged in this order on a GaAs substrate. A capacitor is formed on the first wiring layer. The capacitor includes a lower electrode which has a multi-layer structure consisting of a Ti layer, an Mo layer, and a Pt layer in this order from underside. The capacitor also includes a dielectric film made of strontium titanate. The capacitor further includes an upper electrode which has a multi-layer structure consisting of a WN.sub.x layer (120 um) and a W layer (300 nm) in this order from underside. That surface of the upper electrode, which is in contact with the dielectric film, is defined by the tungsten nitride layer.

Metal oxide capacitor with a WN.sub.X electrode

A metal semiconductor device, in which an electrode is formed on a semiconductor substrate to form a Schottky junction therebetween, and the electrode has an oxide film having a first thickness on its upper surface and a non-oxidized portion having a second thickness from the Schottky junction. A method for producing the metal semiconductor device is also disclosed, in which a conductor layer formed on the semiconductor substrate is oxidized in a gas containing oxygen, and a capless annealing of the semiconductor substrate having the oxidized conductor layer thereon is conducted in an atmosphere containing arsenic.

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Shibuya Tokyo, Japan

Kazuya Nishihori