Seiko Epson Corporation

Kazumasa Hasegawa

Eiji Natori

Tatsuya Shimoda

Masato Shimada

Koichi Oguchi

Hiromu Miyazawa

Takao Nishikawa

Junichi Karasawa

Takamitsu Higuchi

Setsuya Iwashita

Tatsuo Sawasaki

Masayuki Sawada

Masao Nakayama

Tsutomu Nishiwaki

Hiroaki Tamura

Kouji Sumi

Hong Qiu

Hiroyuki Aizawa

Yukihiro Iwasaki

A semiconductor memory device includes a substrate having a semiconductor element formed thereon, an interlayer dielectric layer formed above the substrate, a plug formed in the interlayer dielectric layer, an adhesion layer formed in a region including a region above the plug, and a ferroelectric capacitor formed above the adhesion layer and having a lower electrode, a ferroelectric layer and an upper electrode, wherein an oxidized layer is formed in a part of the adhesion layer at a side wall thereof.

Semiconductor memory device and method for manufacturing the same

A crosspoint-type ferroelectric memory is provided. In the crosspoint-type ferroelectric memory, a first memory cell array and a second memory cell array are stacked with a first interlayer insulating layer and a second interlayer insulating layer therebetween. The first memory cell array includes lower electrodes formed in stripes, upper electrodes formed in stripes in a direction that crosses the lower electrodes, ferroelectric capacitors that are disposed at least at intersecting parts of the lower electrodes and the upper electrodes, and an embedded insulating layer formed between the ferroelectric capacitors. The interlayer insulating layer includes a conductive layer between a first insulating layer and a second insulating layer.

Crosspoint-type ferroelectric memory

A first electrode layer, a first piezoelectric film layer, a second electrode layer, a second piezoelectric film layer, and a third electrode layerare layered in that order on a substrate; these are constrained so as pot to expand or contract in a thickness direction and a piezoelectric transducer is constructed thereby. A plurality of gate linesand, a plurality of data linesandintersecting with the gate lines, and thin film transistorsand, disposed at the intersections of the abovementioned gate lines and data lines, are established; one source-drain of the abovementioned thin film transistors is connected to the abovementioned data lines; another source-drain of the abovementioned thin film transistors is connected to the input sides of the abovementioned thin film piezoelectric transducersthrough; the output sides of the abovementioned thin film piezoelectric transducers are connected to the electrodes of electrophoretic ink display elements; and an electrophoretic ink display apparatus is constructed thereby.

Piezoelectric transducer and electrophoretic ink display apparatus using piezoelectric transducer

A ferroelectric memory device of the present invention includes a memory cell array in which memory cells are arranged in a matrix having first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and a ferroelectric layer disposed at least in intersection regions between the first signal electrodes and the second signal electrodes, and a peripheral circuit section for selectively writing information into or reading information from the memory cell. The memory cell array and the peripheral circuit section are formed in different layers. The peripheral circuit section is formed in a region outside the memory cell array.

Ferroelectric memory device

The present invention relates to a ferroelectric memory having a matrix-type memory cell array which has a superior degree of integration, in which the angularity of the ferroelectric layer's hysteresis curve is improved, the production yield is increased and costs are reduced. A ferroelectric memory having improved angularity in the hysteresis curve, and superior memory characteristics, production yield and costs is realized as follows. Namely, a peripheral circuit chip and a memory cell array chip are engaged onto an inexpensive assembly basesuch as glass or plastic. In memory cell array chipa ferroelectric layer is made to undergo epitaxial growth on to a Si single crystal via a buffer layer and first signal electrode. As a result, a ferroelectric memory can be realized which has improved angularity in the hysteresis curve and superior memory characteristics, production yield, and cost.

Ferroelectric memory and electronic apparatus

A memory cell array is provided that includes ferroelectric capacitors with enhanced characteristics, a method of making the same, and a ferroelectric memory device including the memory cell. In a memory cell array, memory cells including ferroelectric capacitors are arrayed in a matrix. Each ferroelectric capacitor includes a lower electrode, an upper electrode, and a ferroelectric section disposed between the lower electrode and the upper electrode. The ferroelectric section is disposed in an intersection between the lower electrode and the upper electrode. An intermediate electrode is disposed between the ferroelectric sectionand the upper electrode.

Memory cell array including ferroelectric capacitors, method for making the same, and ferroelectric memory device

The present invention relates to: a memory cell array which is capable of decreasing the parasitic capacitance of load capacitance of signal electrodes and has ferroelectric layers making up ferroelectric capacitors and having a predetermined pattern; a method of fabricating the memory cell array, and a ferroelectric memory device. In the memory cell array, memory cells formed of ferroelectric capacitors are arranged in a matrix. The ferroelectric capacitors include first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and ferroelectric layers disposed linearly along either the first signal electrodes or the second signal electrodes. Alternatively, the ferroelectric layers may be disposed only in intersection areas of the first and second signal electrodes.

Memory cell array having ferroelectric capacity, method of manufacturing the same and ferroelectric memory device

A ferroelectric memory device includes a simple matrix type memory cell array. Provided that the maximum absolute value of a voltage applied between a first signal electrode and a second signal electrode is Vs, polarization P of a ferroelectric capacitor formed of the first electrode, the second electrode, and ferroelectric layer is within the range of 0.1P(+Vs)&#x3c;P(&#x2212;1/3Vs) when the applied voltage is changed from +Vs to &#x2212;1/3Vs, and 0.1P(&#x2212;Vs)&#x3e;P(+1/3Vs) when the applied voltage is changed from &#x2212;Vs to +1/3Vs.

A first electrode layera first piezoelectric film layera second electrode layera second piezoelectric film layerand a third electrode layerare layered in that order on a substratethese are constrained so as not to expand or contract in a thickness direction and a piezoelectric transducer is constructed thereby. A plurality of gate linesanda plurality of data linesandintersecting with the gate lines, and thin film transistorsanddisposed at the intersections of the abovementioned gate lines and data lines, are established; one source-drain of the abovementioned thin film transistors is connected to the abovementioned data lines; another source-drain of the abovementioned thin film transistors is connected to the input sides of the abovementioned thin film piezoelectric transducersthroughthe output sides of the abovementioned thin film piezoelectric transducers are connected to the electrodes of electrophoretic ink display elements; and an electrophoretic ink display apparatus is constructed thereby.

A ferroelectric memory device includes a memory cell array and a peripheral circuit section. The memory cell array, in which memory cells are arranged in a matrix, includes first signal electrodes, second signal electrodes which are arranged in a direction so as to intersect the first signal electrodes, and a ferroelectric layer disposed at least at intersection regions between the first signal electrodes and the second signal electrodes. The peripheral circuit section includes circuits for selectively allowing information to be written into or read from the memory cells, such as a first driver circuit, a second driver circuit, and a signal detection circuit. The memory cell array and the peripheral circuit section are disposed in different layers so as to be layered. This ferroelectric memory device can significantly increase the degree of integration of the memory cells and decrease the chip area.

Ferroelectric memory device and method of manufacturing the same

The present invention relates to a ferroelectric memory having a matrix-type memory cell array which has an excellent degree of integration, in which the angularity of the ferroelectric layer's hysteresis curve is improved. A ferroelectric memory having both integration and memory characteristics in which the angularity of the ferroelectric layer's hysteresis curve is improved is realized as follows. Namely, a structure is employed in which the memory cell array and the peripheral circuit are in a plane separated from one another, and the ferroelectric layer is made to undergo epitaxial growth on to a Si single crystal via a buffer and the first signal electrodes.

Ferroelectronic memory and electronic apparatus

A ferroelectric memory device includes memory cells including ferroelectric capacitors formed in regions in which first signal electrodes intersect second signal electrodes. Information is written into a selected memory cell by applying a write voltage between one of the first signal electrodes and one of the second signal electrodes in the memory cell. Information is read from the selected memory cell by applying a read voltage between one of the first signal electrodes and one of the second signal electrodes in the memory cell. Provided that the write voltage is &plusmn;Vs and the read voltage is either &plus;Vs or &minus;Vs, &verbar;Vs&verbar; is less than the absolute value of a saturation voltage at which remanent polarization of the ferroelectric capacitors is saturated.

Ferroelectric memory device and method of operating memory cell including ferroelectric capacitor

A ferroelectric memory device includes a simple matrix type memory cell array. Provided that the maximum absolute value of a voltage applied between a first signal electrode and a second signal electrode is Vs, polarization P of a ferroelectric capacitor formed of the first signal electrode, the second signal electrode, and ferroelectric layer is within the range of 0.1P(&plus;Vs)<P(&minus;&frac13;Vs) when the applied voltage is changed from &plus;Vs to &minus;&frac13;Vs, and 0.1P(&minus;Vs)>P(&plus;&frac13;Vs) when the applied voltage is changed from &minus;Vs to &plus;&frac13;Vs.

Growing community of inventors

Fujimi-cho, Japan

Kazumasa Hasegawa