Nec Corporation

Nec Electronics Corporation

Canon Kabushiki Kaisha

Renesas Electronics Corporation

Kazuhiro Sakaguchi

Yoichi Takaragi

Akio Ito

Yoshihide Terao

Kentaro Saito

Tadashi Hagiuda

Tetsuya Yokoyama

Masao Hayashi

Yutaka Yoshizawa

Provided is a technique capable of improving test efficiency of semiconductor devices. A test apparatus includes a probe card having a plurality of measurement sites that contact with a plurality of semiconductor devices formed on a semiconductor wafer; a control unit configured to generate map information, probe-card form information, and contact-position information, the map information including position information and peculiar information of the semiconductor devices on the semiconductor wafer, the probe-card form information including arrangement information of the measurement sites, the contact-position information indicating a contact position that is a range of the semiconductor device tested at one time by the probe card based on constrained-condition information of limiting contact with the probe card; and a position control unit configured to control a relative position between the probe card and the semiconductor wafer based on the contact-position information.

Test apparatus, test method and recording medium

This invention is to detect defective products of semiconductor devices with high accuracy even when the characteristics of the semiconductor devices vary according to their positions on each of wafers. A screening method includes the steps of measuring respective electrical characteristic values of a plurality of semiconductor devices included in a wafer; acquiring respective positional information of the semiconductor devices over the wafer; subtracting components relatively gently varying over the surface of the wafer, of variations in the electrical characteristic values of the semiconductor devices from the respective electrical characteristic values of the semiconductor devices to thereby correct the respective electrical characteristic values of the semiconductor devices; generating distributions of the post-correction electrical characteristic values with respect to the semiconductor devices; and detecting semiconductor devices in which the post-correction electrical characteristic values assume outliers, out of the semiconductor devices, based on the distributions.

Screening method, screening device and program

A data processing apparatus for processing and protecting data stored in a removable storage medium, including a medium monitoring unit configured to monitor the state of the removable storage medium, an information storage unit configured to store information, and a controller configured to move the data from the removable storage medium to the information storage unit in accordance with the monitoring result of the medium monitoring unit.

Method and apparatus for processing data

An information processing method includes a storing step of storing a correspondence between destination names and e-mail addresses in a storage unit; a setting step of setting a destination name to which a document is to be transmitted; and an upload step of uploading the document to a document management server for a network printing in accordance with an e-mail address corresponding to the set destination name, a document being uploaded to the document management server and then being output in response to an output request from an owner of the e-mail address in the network printing. The uploaded document can be downloaded from the document management server to a printer through a communication medium and can be printed.

Information processing device, information processing method, and control program

An apparatus for sampling a power supply current value for performing frequency analysis of the power supply current flowing in an integrated circuit with a test signal applied to the integrated circuit has a power supply generating a prescribed supply of power for the integrated circuit (DUT: device under test), a current detection means for observing the power supply current value supplied from the power supply to the DUT, a test signal generation means for generating a prescribed test signal to be applied to an input/output terminal other than a power supply terminal of the DUT and for generating a test signal application signal during application of the test signal to the DUT, a sampling means for sampling the power supply current value signal, a sampling time determining means for instructing the sampling means with regard to the start and end timing for sampling, based on the test signal application signal, a sampling data storage means for storing data sampled by the sampling means, a Fourier transform means for performing a Fourier transformation calculation on the sampled data, and a main control means for outputting instructions to various other means and performing overall apparatus control.

Method and apparatus for sampling a power supply current of an integrated circuit, and storage medium onto which is recorded a control program therefor

An observation apparatus according to one embodiment can include a timing generating unit () that generates a timing signal at a predetermined period. A sampling unit () can sample a current observation signal of a power supply current on the basis of the timing signal, and store sampled data in data storing unit (). A data number adjusting unit () can adjust the number of data samples to a number that is a power of two. An arithmetic operating unit () can Fourier-transform the adjusted data to generate frequency spectrum results of the current observation signal. In addition, a failure inspection apparatus according to one embodiment analyzes the frequency spectrum of an integrated circuit under observation to determine a failure condition of the integrated circuit.

Observation and/or failure inspection apparatus, method and program therefor

A method of detecting a failure in an IC, based on spectrum which is a result of analyzing a frequency of a current running through an IC when a test signal is applied to the IC, including (a) assuming that all ICs under test define a under-test IC set, and testing each one of the ICs in the under-test IC set in a conventional manner; (b) removing ICs judged to be in failure in (a), from the under-test IC set; (c) measuring spectrum of a current supplied from a power source into each one of the ICs in the under-test IC set; (d) calculating both a mean value and standard deviation of the spectrum for the under-test IC set; (e) judging whether an IC is in failure, based on both the mean value and the standard deviation of the spectrum; (f) removing ICs judged to be in failure in (e), from the under-test IC set; and (g) judging the undertest IC set to be in no failure.

Method of detecting an integrated circuit in failure among integrated circuits, apparatus of doing the same, and recording medium storing program for doing the same

A unit test signal having duration T is repeatedly supplied from an LSI tester to an IC under test and, simultaneously, a power source current is supplied from the LSI tester through a current detection unit to the IC under test. The power source current is monitored by the current detection unit and a current information obtained by the monitoring is analyzed by a spectrum analyzer unit. Since the repetition period of the test signal is T, the power source current having a period nT flows through the IC under test along with a state shift of the IC under test, where n is an integer. When the IC under test has a fault, the power source current flows with a period n&prime;T, where n&prime; is an integer different from n, or an abnormal power source current flows with the period nT, due to a change of the state shift of the IC under test. A decision unit performs a fault decision of the IC under test by judging an existence of abnormal power source current or the change of the state shift of the IC under test on the basis of values of spectral power in the vicinity of a frequency 1/nT and high harmonics thereof of the power source current or existence or absence of peak having such period.

Integrated circuit fault tester, integrated circuit fault test method and recording medium recorded with fault test control program

Detecting failed integrated circuit among integrated circuits by (a) assuming that all integrated circuits under test define under-test set, and testing each one of the integrated circuits in under-test set, (b) removing integrated circuits judged to be in failure in step (a) from the under-test set, (c) measuring spectrum of a current supplied from power source into each one of integrated circuits in under-test set, (d) calculating both mean value and standard deviation of spectrum for under-test set, (e) judging whether an integrated circuit is in failure or not, based on both the mean value and the standard deviation of the spectrum, (f) removing integrated circuits having been judged to be in failure in step (e) from under-test set, and (g) judging under-test set to be in no failure. Thus, it is possible to find failed integrated circuits without preparing data of integrated circuit in no failure, as a reference.

Detecting failed integrated circuit among integrated circuits, by (a) assuming that all integrated circuits under test define under-test set, and testing each one of the integrated circuits in the under-test set, (b) removing integrated circuits judged to be in failure in step (a) from the under-test set, (c) measuring spectrum of a current supplied from a power source into each one of integrated circuits in under-test set, (d) calculating both mean value and standard deviation of spectrum for under-test set, (e) judging whether an integrated circuit is in failure or not, based on both the mean value and the standard deviation of the spectrum, (f) removing integrated circuits having been judged to be in failure in step (e), from the under-test set, and (g) judging under-test set to be in no failure. Thus, it possible to find failed integrated circuits without preparing data of integrated circuit in no failure, as a reference.

There is provided a method of detecting an integrated circuit in failure among integrated circuits, based on spectrum which is a result of analyzing a frequency of a current running through an integrated circuit when a test signal is applied to the integrated circuit, comprising the steps of (a) assuming that all integrated circuits under test define a under-test integrated circuit set, and testing each one of the integrated circuits in the under-test integrated circuit set in a conventional manner, (b) removing integrated circuits having been judged to be in failure in the step (a), from the under-test integrated circuit set, (c) measuring spectrum of a current supplied from a power source into each one of the integrated circuits in the under-test integrated circuit set, (d) calculating both a mean value and standard deviation of the spectrum for the under-test integrated circuit set, (e) judging whether an integrated circuit is in failure or in no failure, based on both the mean value and the standard deviation of the spectrum, (f) removing integrated circuits having been judged to be in failure in the step (e), from the under-test integrated circuit set, and (g) judging the under-test integrated circuit set to be in no failure. The method makes it possible to find integrated circuits in failure without preparing data of an integrated circuit in no failure, as a reference.

The present invention relates to an image formation system for forming images of read original images, a control method of the image formation system, image formation apparatuses, a storage medium thereof. According to the present invention, sheets of which size corresponds to an attribute of the images are selected, and it is detected whether or not the image formation apparatus has the sheets selected by the image formation apparatus. When it is detected that the image formation apparatus does not have the selected sheets, sheets other than the selected sized sheets are selected as sheets used in forming images by the image formation apparatus, and it is controlled that another image formation apparatus performs an image formation using the sheets other than the selected sized sheets.

Image formation system, control method of image formation system, image formation apparatus and storage medium thereof

A method of screening LSIs is provided, which makes it possible to screen out faulty LSIs before potential failure existing therein is elicited. A specific power supply voltage is supplied to LSIs to be tested while applying a specific test signal to the LSIs at a specific period. Power supply currents of the LSIs are observed. Sets of power spectrum data of the power supply currents are generated corresponding to the test signal. The distributions of the sets of power spectrum data are generated. whether or not the distributions of the sets of power spectrum data of the power supply currents are equal to or greater than a specific reference value is judged. When the distribution of the set of power spectrum data of the power supply current of one of the devices is equal is to or greater than the reference value, the device in question is regarded as a faulty one.

Screening of semiconductor integrated circuit devices

In an LSI testing apparatus, a test sequence generator produces at least one sequence of test signals each having a different test pattern. A source current sensor detects a source current flowing from a power voltage source to an integrated circuit device under test when the device is subjected to the sequence of test signals. Counter circuitry defines a window period equal to at least one sequence of the test signals. Analog-to-digital converter circuitry is activated during the window period to sample the source current and quantize sampled values of the source current to digital samples. A discrete Fourier transform analyzer analyzes the digital samples to produce a number of spectral values at frequencies k/T, where T represents the period of said sequence and k is an integer equal to or greater than unity. Decision circuitry makes a decision on the analyzed spectral values using a plurality of reference spectral values.

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Tokyo, Japan

Kazuhiro Sakaguchi