Hamamatsu-photonics K.k.

Kazuhiro Hotta

Takafumi Higuchi

Akira Shimase

Tomochika Takeshima

Hirotoshi Terada

Toshiyuki Majima

Masahiro Takeda

A semiconductor apparatus examination method includes a step of acquiring a first interference waveform based on signals from a plurality of drive elements according to light from a first light beam spot including the plurality of drive elements in a semiconductor apparatus, a step of acquiring a second interference waveform based on signals from the plurality of drive elements according to light from a second light beam spot having a region configured to partially overlap the first spot and including the plurality of drive elements, and a step of separating a waveform signal for each of the drive elements in the first and second spots based on the first and second interference waveforms.

Semiconductor apparatus examination method and semiconductor apparatus examination apparatus

A semiconductor inspection method by an observation system includes a step of acquiring a first pattern image showing a pattern of a semiconductor device, a step of acquiring a second pattern image showing a pattern of the semiconductor device and having a different resolution from a resolution of the first pattern image, a step of learning a reconstruction process of the second pattern image using the first pattern image as training data by machine learning, and reconstructing the second pattern image into a reconstructed image having a different resolution from a resolution of the second pattern image by the reconstruction process based on a result of the learning, and a step of performing alignment based on a region calculated to have a high degree of certainty by the reconstruction process in the reconstructed image and the first pattern image.

Method for inspecting semiconductor and semiconductor inspecting device

An observation system includes a detector that detects light from a semiconductor device and outputs a detection signal, a 2D camera, an optical device that guides light to the detector and the 2D camera, an image processing unit that generates a first optical image of the semiconductor device based on the detection signal and receives an input of a first CAD image, an image analysis unit that learns a conversion process of the first CAD image by machine learning using the first optical image as training data, and converts the first CAD image into a second CAD image resembling the first optical image by the conversion process based on a result of the learning, and an alignment unit that performs alignment based on a second optical image and the second CAD image.

Semiconductor inspection device and semiconductor inspection method

A semiconductor device examination method includes a step of acquiring a first interference waveform based on signals from a plurality of drive elements according to light from a first light beam spot including the plurality of drive elements in a semiconductor device, a step of acquiring a second interference waveform based on signals from the plurality of drive elements according to light from a second light beam spot having a region configured to partially overlap the first spot and including the plurality of drive elements, and a step of separating a waveform signal for each of the drive elements in the first and second spots based on the first and second interference waveforms.

Semiconductor device examination method and semiconductor device examination device

An inspection apparatus includes a light sensor that detects light from a semiconductor device to which an electric signal has been input, an optical system that guides light from the semiconductor device to the light sensor, and a control device electrically connected to the light sensor. The control device includes a measurement unit that acquires waveform data obtained by optical measurement for each of a plurality of positions on a defective semiconductor device and waveform data obtained by the optical measurement for each of a plurality of positions on a non-defective semiconductor device, a calculation unit that calculates a degree of correspondence between the waveform data of the defective semiconductor device and the waveform data of the non-defective semiconductor device, and an analysis unit that analyzes a defective part of the defective semiconductor device on the basis of the degree of correspondence for each of the plurality of positions.

Analysis method, analysis device, analysis program, and recording medium for recording analysis program

A semiconductor device inspection apparatus includes: a light sensor that detects light from a semiconductor device as a DUT to which an electric signal has been input; an optical system that guides light from the semiconductor device to the light sensor; and a control device electrically connected to the light sensor. The control device includes: a data reading unit that reads mask data indicating a mask layout of the semiconductor device; a search unit that searches for a position of a transistor in the semiconductor device on the basis of polygon data of a gate layer of the semiconductor device included in the mask data; a setting unit that sets the searched position of the transistor as an optical measurement target position; and a measurement unit that performs optical measurement for the set optical measurement target position to acquire a measurement result.

Optical measurement method, optical measurement device, optical measurement program, and recording medium for recording optical measurement program

An image processing method includes a step of acquiring a measured image Gmeasured from a semiconductor device S and a first pattern image Gshowing a pattern of the semiconductor device S, a step of acquiring a reference measured image Gmeasured from a reference semiconductor device SR being the semiconductor device S or a semiconductor device different from the semiconductor device S and a second pattern image Gshowing a pattern of the reference semiconductor device SR, a step of acquiring matching information indicating a correlation of the first pattern image Gand the second pattern image G, and a step of determining a difference of the measured image Gand the reference measured image Gbased on the matching information to acquire a comparative image G.

Image processing method, image processing system, and storage medium storing image processing program

An image processing method in an observation systemA includes a step of acquiring a measured image Gmeasured from a semiconductor device S and a first pattern image Gshowing a pattern of the semiconductor device S corresponding to the measured image G, a step of acquiring a second pattern image Gshowing a pattern of the semiconductor device S, a step of acquiring matching information indicating a correlation of the first pattern image Gand the second pattern image Gbased on the first pattern image Gand the second pattern image G, and a step of superimposing the second pattern image Gand the measured image Gbased on the matching information to acquire a superimposed image G.

A failure analysis apparatusis composed of an inspection information acquirerfor acquiring a failure observed image Pof a semiconductor device, a layout information acquirerfor acquiring layout information, and a failure analyzerfor analyzing a failure. The failure analyzerextracts as a candidate interconnection for a failure, an interconnection passing an analysis region, out of a plurality of interconnections, using interconnection information to describe a configuration of interconnections in the semiconductor device by a pattern data group of interconnection patterns in respective layers, and, for extracting the candidate interconnection, it performs an equipotential trace of the interconnection patterns using the pattern data group, thereby extracting the candidate interconnection. This substantializes a semiconductor failure analysis apparatus, failure analysis method, and failure analysis program capable of securely and efficiently performing the analysis of the failure of the semiconductor device using the failure observed image.

Semiconductor failure analysis apparatus which acquires a failure observed image, failure analysis method, and failure analysis program

A failure analysis apparatusis composed of an inspection information acquirerfor acquiring a failure observed image Pof a semiconductor device, a layout information acquirerfor acquiring layout information, and a failure analyzerfor analyzing a failure. The failure analyzerextracts candidate nets passing at least one of analysis regions set from the failure observed image, out of a plurality of nets in the semiconductor device, and passage counts of the respective candidate nets through the analysis regions, selects a candidate net with the largest passage count as a first failure net, and selects a second failure net with attention to analysis regions where the first failure net does not pass. This substantializes a semiconductor failure analysis apparatus, failure analysis method, and failure analysis program capable of securely and efficiently performing the analysis of the failure of the semiconductor device using the failure observed image.

Semiconductor failure analysis apparatus, failure analysis method, and failure analysis program

A failure analysis apparatusis composed of an inspection information acquirerfor acquiring at least a pattern image Pof a semiconductor device, a layout information acquirerfor acquiring a layout image P, a failure analyzerfor analyzing a failure of the semiconductor device, and an analysis screen display controllerfor letting a display devicedisplay information about the failure analysis. The analysis screen display controllergenerates a superimposed image in which the pattern image Pand the layout image Pare superimposed, as an image of the semiconductor device to be displayed by the display device, and sets a transmittance of the layout image Prelative to the pattern image Pin the superimposed image. This substantializes a semiconductor failure analysis apparatus, analysis method, analysis program, and analysis system capable of securely and efficiently carrying out the analysis of the failure of the semiconductor device.

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Hamamatsu, Japan

Kazuhiro Hotta