Shinko Electric Industries Co., Ltd.

Kazuhiko Ooi

Tadashi Kodaira

Shunichiro Matsumoto

Jyunichi Nakamura

Eisaku Watari

Masaru Yamazaki

Takaaki Yazawa

Yukiji Watanabe

To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.

Package for semiconductor devices

To prevent the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a small strength. A package for semiconductor devices is formed as a laminate () of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole regions or some regions of the insulating resin layers (to) of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.

A metal core substrate comprises a core layer ( ) consisting of first and second metal plates ( ) layered with a third insulating layer ( ) interposed therebetween; first and second insulating layers ( ) formed on the first and metal plates, respectively; first and second wiring patterns ( ) formed on the first and second insulating layers, respectively. A conductive layer ( ) formed in a through-hole ( ) penetrates the first insulating layer, the first metal plate, the third insulating layer, the second metal plate and the second insulating layer for electrically connecting the first wiring pattern with the second wiring pattern. The first metal plate ( ) is electrically connected with the first wiring pattern ( ) and the second wiring pattern ( ), respectively, by means of a via ( ) and by means a via ( ). The second metal plate ( ) is electrically connected with the second wiring pattern ( ) and the first wiring pattern ( ), respectively, by means of a via ( ) and by means a via ( ), respectively.

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Nagano, Japan

Kazuhiko Ooi