Texas Instruments Corporation

Kayvan Sadra

Theodore Warren Houston

Amitava Chatterjee

Seetharaman Sridhar

Alwin J Tsao

Shyh-Horng Yang

Yaojian Leng

Thomas J Aton

Freidoon Mehrad

Youn Sung Choi

Shaoping Tang

Gregory Charles Baldwin

Zhijian Lu

Guohong Zhang

Robert Soper

Jong Shik Yoon

Oluwamuyiwa Oluwagbemiga Olubuyide

An integrated circuit (IC) die has an on-die parametric test module. A semiconductor substrate has die area, and a functional IC formed on an IC portion of the die area including a plurality of circuit elements configured for performing a circuit function. The on-die parametric test module is formed on the semiconductor substrate in a portion of the die area different from the IC portion. The on-die parametric test module includes a reference layout that provides at least one active reference MOS transistor, wherein the active reference MOS transistor has a reference spacing value for each of a plurality of context dependent effect parameters. A plurality of different variant layouts are included on the on-die parametric test module. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing value for at least one of the context dependent effect parameters.

On-die parametric test modules for in-line monitoring of context dependent effects

A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region () on a surface of a substrate having a first concentration of a first conductivity type (P-well). A gate region () having a length and a width is formed on the dielectric region. Source () and drain () regions having a second conductivity type (N+) are formed in the substrate on opposite sides of the gate region. A first impurity region () having the first conductivity type (P+) is formed adjacent the source. The first impurity region has a second concentration greater than the first concentration.

SRAM cell with asymmetrical pass gate

The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

Application of different isolation schemes for logic and embedded memory

Methods are disclosed for forming an SRAM cell having symmetrically implanted active regions and reduced cross-diffusion therein. One method comprises patterning a resist layer overlying a semiconductor substrate to form resist structures about symmetrically located on opposite sides of active regions of the cell, implanting one or more dopant species using a first implant using the resist structures as an implant mask, rotating the semiconductor substrate relative to the first implant by about 180 degrees, and implanting one or more dopant species into the semiconductor substrate with a second implant using the resist structures as an implant mask. A method of performing a symmetric angle implant is also disclosed to provide reduced cross-diffusion within the cell, comprising patterning equally spaced resist structures on opposite sides of the active regions of the cell to equally shadow laterally opposed first and second angled implants.

Intentional pocket shadowing to compensate for the effects of cross-diffusion in SRAMs

A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabrication of asymmetrical pass transistors comprises forming a dielectric region on a surface of a substrate having a first conductivity type. A gate region having a length and a width is formed on the dielectric region. Source and drain extension regions having a second conductivity type are formed in the substrate on opposite sides of the gate region. A first pocket impurity region having a first concentration and the first conductivity type is formed adjacent the source. A second pocket impurity region having a second concentration and the first conductivity type may be formed adjacent the drain. If formed, the second concentration is smaller than the first concentration, reducing the gate induced drain leakage current.

SRAM cell with asymmetrical transistors for reduced leakage

According to one embodiment, a method for patterning a set of features for a semiconductor device includes providing a mask including a substrate and at least one pair of first and second main features disposed on a substrate. The method also includes positioning the mask over a layer of light-sensitive material, and exposing the mask to a light source. The mask also includes at least one sub-resolution feature connecting the first and second main features.

Method and system for contiguous proximity correction for semiconductor masks

A method of placing a cell in an array is disclosed. The method includes placing the cell a plurality of times () in a first array. The cell is also placed a plurality of times () in a second array. The second array is placed adjacent and offset from the first array by an offset distance (O).

Staggered memory cell array

Methods () are disclosed for minimizing the effect of pocket shadowing in the fabrication of an angled pocket implant () extending underlying a gate region () of a transistor (), particularly in SRAM devices (). The pocket shadowing is minimized by initially forming a relatively thick resist layer () overlying the semiconductor device (), then the resist layer thickness () is reduced (trimmed) to a reduced thickness () by using a subsequent post-development dry or wet resist-reduction etch process (). The etch process () also increases corner rounding (), thereby reducing pocket shadowing of the angled implant from nearby features or the resist (). The pocket shadow reduction may be accomplished by first forming () the relatively thick resist layer () overlying the semiconductor device (). The resist layer () is then wet and/or dry etched () to trim the resist thickness () and to round the corners () of the resist (). In combination, these changes reduce shadowing of angled implants from nearby structures and resist edges. The method may further comprise a first implant () (e.g., an LDD implant) before the resist etch trim (), and a second angled pocket implant () after the etch trim () to permit individually optimizing the resist thickness and CD for each implant. Thus, only one lithography step is required, while cross diffusion of the LDD implant is mitigated. Transistors (and, orand) formed in this manner may yield improved performance when incorporated into SRAM () since the probability that such transistors will be more closely matched is increased.

Application of post-pattern resist trim for reducing pocket-shadowing in SRAMs

Photo reticles () are formed comprising a first and second printable features (), () which are connected by a channel assist feature (). The size of the channel assist feature is such that the channel assist feature will not substantially print on photoresist that is exposed using the reticle. Third printable features () can be placed a distance Wfrom the channel assist feature (). The channel assist feature will assist in the formation of the third printable feature ().

Photo reticles using channel assist features

A method for measuring the step height of a STI structure is described. The method involves measuring the change in resistance of a polysilicon structure as the step height changes. The resistance of the polysilicon structure is measured by applying a voltage and measuring the resulting current.

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Addison, TX, United States of America

Kayvan Sadra