International Business Machines Corporation

Infineon Technologies Ag

Tokyo Electron Limited

Samsung Electronics Co., Ltd.

Advanced Micro Devices Corporation

Chartered Semiconductor Manufacturing Ltd (corporation)

Kaushik Arun Kumar

Lawrence Alfred Clevenger

Timothy Joseph Dalton

Kevin Shawn Petrarca

Andrew Herbert Simon

Douglas C La Tulipe, Jr

Steffen K Kaldor

Christy Sensenich Tyberg

Kelly Malone

Mark Hoinkis

Chih-Chao Yang

Dureseti Chidambarrao

Erdem Kaltalioglu

Stephan Grunow

Jochen Schacht

Carl John Radens

Shyng-Tsong Chen

Huilong Zhu

Elbert Emin Huang

Omer H Dokumaci

Michael Ray Sievers

Andy Cowley

Andres Fernando Munoz

Alok Ranjan

Dirk Pfeiffer

Terry Allen Spooner

Yun-Yu Wang

Muthumanickam Sankarapandian

David Lee Rath

Chandrasekhar Narayan

Vidhya Ramachandran

Wei-Tsu Tseng

Richard Stephen Wise

Andrew P Cowley

Larry Clevenger

Karl W Barth

Kangguo Cheng

Clement Hsingjen Wann

Shom Ponoth

Katherine Lynn Saenger

Richard Stephan Wise

Sandra Guy Malhotra

Johnathan E Faltermeier

Michael P Belyansky

Akiteru Ko

Mahadevaiyer Krishnan

Shahab Siddiqui

Michael F Lofaro

Chao-Kun Hu

Judith Marie Rubino

Kenneth M Davis

Fen Fen Jamin

Anthony David Lisi

Sean P E Smith

Ramona Kei

Vidhya Chakrapani

Theodorus E Standaert

Oleg Gluschenkov

Haining S Yang

Anton J deVillers

Sampath Purushothaman

Soon-Cheon Seo

Matthew Earl Colburn

Roy Rongqing Yu

Richard Paul Volant

Griselda Bonilla

Kandabara N Tapily

Satyanarayana Venkata Nitta

Stephen Mark Rossnagel

Jeffrey Curtis Hedrick

Roger Allan Quon

Stephen Edward Greco

Hermann Wendt

Eiji Suzuki

Nicholas C M Fuller

David L O'Meara

Michael Wayne Lane

Andrew W Metz

Ahmad D Katnani

Ravi Prakash Srivastava

Hiroto Ohtake

Habib Hichri

Catherine B Labelle

Stefanie Ruth Chiras

William G America

Wan-jae Park

Markus Naujok

Douglas La Tulipe

Yi-Hsiung Lin

Narender N Rana

Hakeem B S Akinmade-Yusuff

Yusuke Ohsawa

John Charles Petrus

Heidi Lee Baks

Richard H Gaylord

Nicholas Colvin Masi Fuller

Robert Rosenburg

Blaze J Messer

Joseph Edward Linville

Hakeem S B Akinmade-Yusuff

Embodiments of the invention provide a processing method for bottom-up deposition of a film in a recessed feature. According to one embodiment, the method includes a) providing a substrate containing a recessed feature having a bottom and a sidewall, b) depositing a film on the bottom and on the sidewall of the recessed feature, and c) covering the film at the bottom of the recessed feature with a mask layer. The method further includes d) etching the film from the sidewall, and e) removing the mask layer to expose the film at the bottom of the recessed feature. Steps b)-e) may be repeated at least once until the film at the bottom of the recessed feature has a desired thickness. In one example, the recessed feature may be filled with the film.

Method for bottom-up deposition of a film in a recessed feature

Methods for using high-speed EUV resists including resists having additives that may be detrimental to etch chambers. Methods include using reversal materials and/or reversal techniques, as well as diffusion-limited etch-back and slimming for pattern creation and transfer. A substrate with high-speed EUV resist is lithographically patterned and developed into a patterned resist mask. An image reversal material is then over-coated on the patterned resist mask such that the image reversal material fills and covers the patterned resist mask. An upper portion of the image reversal material is removed such that top surfaces of the patterned resist mask are exposed. The patterned resist mask is removed such that the image reversal material remains resulting in a patterned image reversal material mask. Residual resist material is removed via a slimming process using an acid diffusion and subsequent development.

Method for using post-processing methods for accelerating EUV lithography

A method for preparing a patterned directed self-assembly layer for reducing directed self-assembly pattern defectivity using direct current superpositioning is provided. A substrate having a block copolymer layer overlying a first intermediate layer, said block copolymer layer comprising a first phase-separated polymer defining a first pattern and a second phase-separated polymer defining a second pattern in said block copolymer layer is provided. A first plasma etching process using plasma formed of a first process composition to remove said second phase-separated polymer while leaving behind said first pattern of said first phase-separated polymer is performed. A second plasma etching process to transfer said first pattern into said first intermediate layer using plasma formed of a second process composition is performed. In an embodiment, said first phase-separated polymer is exposed to an electron beam preceding, during, or following said first plasma etching process, or preceding or during said second plasma etching process.

Etch process for reducing directed self assembly pattern defectivity using direct current positioning

Provided is a method for preparing a patterned directed self-assembly layer, comprising: providing a substrate having a block copolymer layer comprising a first phase-separated polymer defining a first pattern in the block copolymer layer and a second phase-separated polymer defining a second pattern in the block copolymer layer; and performing an etching process to selectively remove the second phase-separated polymer while leaving behind the first pattern of the first phase-separated polymer on the surface of the substrate, the etching process being performed at a substrate temperature less than or equal to about 20 degrees C. The method further comprises providing a substrate holder for supporting the substrate, the substrate holder having a first temperature control element for controlling a first temperature at a central region and second temperature control element at an edge region of the substrate and setting a target value for the first and the second temperature.

Etch process for reducing directed self assembly pattern defectivity

A method of etching an aluminum-containing layer on a substrate is described. The method includes forming plasma from a process composition containing a halogen element, and exposing the substrate to the plasma to etch the aluminum-containing layer. The method may additionally include exposing the substrate to an oxygen-containing environment to oxidize a surface of the aluminum-containing layer and control an etch rate of the aluminum-containing layer. The method may further include forming first plasma from a process composition containing HBr and an additive gas having the chemical formula CHR(wherein R is a halogen element, x and y are equal to unity or greater, and z is equal to zero or greater), forming second plasma from a process composition containing HBr, and exposing the substrate to the first plasma and the second plasma to etch the aluminum-containing layer.

Dry metal etching method

A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from the gate structure and the substrate, while retaining a sidewall spacer positioned along a sidewall of the gate structure. The spacer etch process sequence may include depositing a SiOCl-containing layer on an exposed surface of the spacer material to form a spacer protection layer.

Formation of SiOCl-containing layer on spacer sidewalls to prevent CD loss during spacer etch

A method of forming a semiconductor device. A substrate having first and second materials is provided, wherein the second material is occluded by the first material. The substrate is etched using a first non-plasma etch process that etches the first material at a higher rate relative to a rate of etching the second material. The first non-plasma etch process exposes the second material that is overlying at least a portion of the first material. The second material is then etched using a plasma containing a reactive gas, which exposes the at least a portion of the first material. The first material including the at least a portion of the first material that was exposed by etching the second material are etched using a second non-plasma etch process.

Combined silicon oxide etch and contamination removal process

A method for protecting an exposed low-k surface is described. The method includes receiving a substrate having a mask layer and a low-k layer formed thereon, wherein a pattern formed in the mask layer using a lithographic process has been transferred to the low-k layer using an etching process to form a structural feature therein. Additionally, the method includes forming a SiOCl-containing layer on exposed surfaces of the mask layer and the low-k layer, and anisotropically removing the SiOCl-containing layer from a top surface of the mask layer and a bottom surface of the structural feature in the low-k layer, while retaining a remaining portion of the SiOCl-containing layer on sidewall surfaces of the structural feature. The method further includes performing an ashing process to remove the mask layer, and thereafter, selectively removing the remaining portion of the SiOCl-containing layer from the sidewall surfaces of the structural feature.

Formation of SiOCl-containing layer on exposed low-k surfaces to reduce low-k damage

A method for method for removing a hard mask is described. The method includes forming at least a portion of a trench-via structure in a low-k insulation layer on a substrate using one or more etching processes and a hard mask layer overlying the low-k insulation layer. Thereafter, the method includes depositing a SiOCl-containing layer on exposed surfaces of the trench-via structure to form an insulation protection layer, performing one or more etching processes to anisotropically remove at least a portion of the SiOCl-containing layer from at least one surface on the trench-via structure, and removing the hard mask layer using a mask removal etching process.

Sidewall and chamfer protection during hard mask removal for interconnect patterning

A semiconductor structure fabrication method. A provided structure includes: a semiconductor substrate, a transistor on the semiconductor substrate, N interconnect layers on the semiconductor substrate, and a temporary filling region within the N layers. N is at least 2. The temporary filling region is heated at a high temperature sufficiently high to result in the temporary filling material being replaced by a cooling pipes system that does not include any solid or liquid material. A first portion and a second portion of the cooling pipes system are each in direct physical contact with a surrounding ambient at a first interface and a second interface respectively such that a first direction perpendicular to the first interface is perpendicular to a second direction perpendicular to the second interface. A totality of interfaces between the cooling pipes system and the ambient consists of the first interface and the second interface.

On-chip cooling for integrated circuits

A method of forming a semiconductor device includes patterning a photoresist layer formed over a homogeneous semiconductor device layer to be etched; subjecting the semiconductor device to an implant process that selectively implants a sacrificial etch stop layer that is self-aligned in accordance with locations of features to be etched within the homogeneous semiconductor device layer, and at a desired depth for the features to be etched; etching a feature pattern defined by the patterned photoresist layer into the homogenous semiconductor device layer, stopping on the implanted sacrificial etch stop layer; and removing remaining portion of the implanted sacrificial etch stop layer prior to filling the etched feature pattern with a fill material.

Self-aligned patterned etch stop layers for semiconductor devices

Structures and methods for forming the same. A semiconductor chip includes a substrate and a transistor. The chip includes N interconnect layers on the substrate, N being a positive integer. The chip includes a cooling pipes system inside the N interconnect layers. The cooling pipes system does not include any solid or liquid material. Given any first point and any second point in the cooling pipes system, there exists a continuous path which connects the first and second points and which is totally within the cooling pipes system. A first portion of the cooling pipes system overlaps the transistor. A second portion of the cooling pipes system is higher than the substrate and lower than a top interconnect layer. The second portion is in direct physical contact with a surrounding ambient.

On-chip cooling systems for integrated circuits

Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically insulating layer. First and second portions of the electrically insulating layer extending opposite the first and second openings, respectively, are simultaneously etched at first and second different etch rates. This etching yields a first trench extending adjacent the first opening that is deeper than a second trench extending adjacent the second opening. Then, the bottoms of the first and second trenches are simultaneously etched to substantially the same depths using an etching process that compensates for the first and second different etch rates.

Methods of patterning insulating layers using etching techniques that compensate for etch rate variations

A method of forming a trench in a semiconductor device formed of a substrate and a first layer formed over the substrate includes forming an initial trench that passes through the first layer to the substrate, the initial trench having a diameter that decreases from a first diameter to a second diameter, the second diameter being measured at a distance closer to the substrate than the first diameter; exposing the trench to a dopant via an orthogonal ion implant to form doped regions sidewalls of the trench; and etching the trench to remove at least some of the doped regions.

Liner protection in deep trench etching

A technique is described whereby temperature gradients are created within a semiconductor wafer. Temperature sensitive etching and/or deposition processes are then employed. These temperature sensitive processes proceed at different rates in regions with different temperatures. To reduce pinch off in etching processes, a temperature sensitive etch process is selected and a temperature gradient is created between the surface and subsurface of a wafer such that the etching process proceeds more slowly at the surface than deeper in the wafer. This reduces 'crusting' of solid reaction products at trench openings, thereby eliminating pinch off in many cases. Similar temperature-sensitive deposition processes can be employed to produce void-free high aspect ratio conductors and trench fills.

Thermal gradient control of high aspect ratio etching and deposition processes

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Kaushik Arun Kumar