Sanyo Electric Co., Ltd.

Semiconductor Components Industries, LLC

Katsuyoshi Anzai

Masafumi Uehara

Shuichi Kikuchi

Eiji Nishibe

Toshihiro Hachiyanagi

A transistor structure that improves ESD withstand voltages is offered. A high impurity concentration drain layer is formed in a surface of an intermediate impurity concentration drain layer at a location separated from a drain-side end of a gate electrode. And a P-type impurity layer is formed in a surface of a substrate between the gate electrode and the high impurity concentration drain layer so as to surround the high impurity concentration drain layer. When a parasitic bipolar transistor is turned on by an abnormal surge, electrons travel from a source electrode to a drain electrode. Here, electrons travel dispersed in the manner to avoid a vicinity X of the surface of the substrate and travel through a deeper path to the drain electrode as indicated by arrows in FIG.

Semiconductor device having drain/source surrounded by impurity layer and manufacturing method thereof

A withstand voltage against electrostatic discharge of a high voltage MOS transistor is improved. An N-type drain layer is not formed under an N-type drain layer, while a P-type buried layer is formed in a region under the N-type drain layer. A PN junction of high impurity concentration is formed between the N-type drain layer and the P-type buried layer. In other words, a region having low junction breakdown voltage is formed locally. The surge current flows through the PN junction into the silicon substrate before the N-type drain layer below a gate electrode is thermally damaged. Hence, the ESD withstand voltage is improved.

Manufacturing method of semiconductor device with protection against electrostatic discharge

Semiconductor device

Growing community of inventors

Oizumi-machi, Japan

Katsuyoshi Anzai