Fujitsu Semiconductor Limited

Katsuya Ogata

Toshio Hino

Tsuyoshi Sakata

Yutaka Mizuno

Takanori Hiramoto

Hiroyuki Rokugawa

A plurality of gate electrode patterns to be laid out in parallel are alternately set as first patterns to be formed in a first exposure step of double patterning and as second patterns to be formed in a second exposure step. Subsequently, a circuit that includes transistor pairs each formed by connecting one of the first patterns and one of the second patterns in parallel is laid out. This reduces the risk of variations in characteristics of transistors caused by double patterning.

Layout method and method of manufacturing semiconductor device

A design support apparatus includes: a circuit-data generation unit to generate circuit data based on layout information of a semiconductor integrated circuit; and a parameter determination unit to set a first parameter relating to mechanical stress exerted on a transistor including at least one of a plurality of gates in a diffusion region, wherein the circuit-data generation unit obtains a mobility of the transistor based on the first parameter and reflects the mobility in the circuit data.

Growing community of inventors

Yokohama, Japan

Katsuya Ogata