Mitsubishi Electric Corporation

Katsutoshi Sugawara

Yutaka Fukui

Rina Tanaka

Yasuhiro Kagawa

Hideyuki Hatta

Kohei Adachi

Kazuya Konishi

Yusuke Miyata

Shiro Hino

Naruhisa Miura

Hidenori Koketsu

Takeharu Kuroiwa

Atsushi Narazaki

Nobuo Fujiwara

Kensuke Taguchi

Kazuya Ishibashi

A semiconductor device has a cell region, a dividing region dividing the cell region in an expanding direction of a stacking fault band, and a termination region, and includes in a dividing region, a semiconductor layer including a drift region of a first conductivity type and a second well region of a second conductivity type provided in an upper portion of the drift region, a second interlayer insulating film provided on the semiconductor layer, and a source electrode provided on the second interlayer insulating film. The second interlayer insulating film has two second contact holes aligned in an expanding direction of stacking fault band and electrically connecting the source electrode to the second well region. The second well region is formed as one region continuous in the expanding direction of stacking fault band in the region interposed between the two second contact holes in top view.

Semiconductor device and power conversion apparatus

The present invention relates to a semiconductor device having trench gates. The semiconductor device includes the following: a first semiconductor layer; a first semiconductor region selectively disposed in the upper layer of the first semiconductor layer; a second semiconductor region in contact with the first semiconductor region; a third semiconductor region on the bottom surfaces of the first and second semiconductor regions; gate trenches provided to penetrate the first and third semiconductor regions in the thickness direction of the first and third semiconductor regions to reach the inside of the first semiconductor layer; a field-reducing region on the bottom of each gate trench; and connection layers arranged in the first semiconductor layer at intervals so as to be each in contact with at least one of sidewalls of the gate trenches, the connection layers each electrically connecting the field-reducing region to the third semiconductor region.

Semiconductor device and power converter

An object of the present disclosure is to suppress decrease in withstand voltage and increase in ON voltage and to increase body diode current. An SiC-MOSFET includes: a source region formed on a surface layer of a base region; a gate electrode facing a channel region which is a region of the base region sandwiched between a drift layer and the source region via a gate insulating film; a source electrode having electrically contact with the source region; and a plurality of first embedded regions of a second conductivity type formed adjacent to a lower surface of the base region. The plurality of first embedded regions are formed immediately below at least both end portions of the base region, and three or more first embedded regions are formed to be separated from each other.

SiC-mosfet

An object is to provide a technique capable of reducing a parasitic capacitance in a semiconductor device with high accuracy. A semiconductor device includes: a base region; a source region; a second trench passing through the base region to reach the drift layer; a second protective layer disposed in a bottom portion of the second trench; a source electrode, at least part of which is disposed in the second trench, to be electrically connected to a first protective layer, the base region, and the source region; and a source side connection layer of a second conductivity type constituting at least part of a lateral portion of the second trench and connected to the base region and the second protective layer.

Semiconductor device

The present invention relates to a silicon carbide semiconductor device that includes a Schottky barrier diode in a field-effect transistor and includes a first trench provided through first and second semiconductor regions in a thickness direction and reaches inside a semiconductor layer, a second trench provided through the second semiconductor region in the thickness direction and reaches inside the semiconductor layer, a gate electrode embedded in the first trench via a gate insulating film, a Schottky barrier diode electrode embedded in the second trench, a first low-resistance layer having contact with a trench side wall of the first trench, and a second low-resistance layer having contact with a trench side wall of the second trench. The second low-resistance layer has an impurity concentration that is higher than the impurity concentration in the semiconductor layer and lower than the impurity concentration in the first low-resistance layer.

Silicon carbide semiconductor device and power converter

A drift layer is made of silicon carbide and has a first conductivity type. At least one trench has a first side surface facing a Schottky barrier diode region, and a second side surface extending in a transistor region and contacting a source region, a body region, and the drift layer. A first protective region is provided under the at least one trench, has a second conductivity type, and is higher in impurity concentration of the second conductivity type than the body region. A second protective region extends from the first protective region, reaches at least one of the first side surface and an end region of the second side surface continuous with the first side surface, has an uppermost portion shallower than a lowermost portion of the body region, and is higher in impurity concentration of the second conductivity type than the body region.

Silicon carbide semiconductor device and method of manufacturing same

A semiconductor device includes a trench-type switching element formed in an active region and a trench-type current sense element formed in a current sense region. Below a trench in which a gate electrode of the switching element is embedded, a trench in which a gate electrode of the current sense element is embedded, and a trench formed at the boundary portion between the active region and the current sense region, protective layers are formed, respectively. The protective layer at the boundary portion between the active region and the current sense region has a divided portion that is divided in a direction from the active region to the current sense region.

A drift layer is formed of silicon carbide and has a first conductivity type. A trench bottom protective layer is provided on a bottom portion of a gate trench and has a second conductivity type. A depletion suppressing layer is provided between a side surface of the gate trench and the drift layer, extends from a lower portion of a body region up to a position deeper than the bottom portion of the gate trench, has the first conductivity type, and has an impurity concentration of the first conductivity type higher than that of the drift layer. The impurity concentration of the first conductivity type of the depletion suppressing layer is reduced as the distance from the side surface of the gate trench becomes larger.

Silicon carbide semiconductor device, power converter, method of manufacturing silicon carbide semiconductor device, and method of manufacturing power converter

A silicon carbide semiconductor device includes a diffusion protective layer provided below a gate insulating film, a gate line provided on an insulation film on the bottom face of a terminal trench and electrically connected to a gate electrode, the terminal trench being located more toward the outer side than the gate trench, a gate pad joined to the gate line in the terminal trench, a terminal protective layer provided below the insulation film on the bottom face of the terminal trench, and a source electrode electrically connected to a source region, the diffusion protective layer, and the terminal protective layer. The diffusion protective layer has first extensions that extend toward the terminal protective layer and that are separated from the terminal protective layer. This configuration inhibits an excessive electric field from being applied to the gate insulating film provided on the bottom face of the gate trench.

A drift layer has a first conductivity type. A well region has a second conductivity type. A well contact region has a resistivity lower than that of the well region. A source contact region is provided on the well region, separated from the drift layer by the well region, and has the first conductivity type. A source resistance region is provided on the well region, separated from the drift layer by the well region, is adjacent to the source contact region, has the first conductivity type, and has a sheet resistance higher than that of the source contact region. A source electrode contacts the source contact region, the well contact region, and the source resistance region, and is continuous with the channel at least through the source resistance region.

A drift layer made of silicon carbide has a first conductivity type. A body region on the drift layer has a second conductivity type. A source region on the body region has the first conductivity type. A gate insulating film is on each inner wall of at least one trench. A protective layer has at least a portion below the trench, is in contact with the drift layer, and has the second conductivity type. A first low-resistance layer is in contact with the trench and the protective layer, straddles a border between the trench and the protective layer in the depth direction, has the first conductivity type, and has a higher impurity concentration than the drift layer. A second low-resistance layer is in contact with the first low-resistance layer, is away from the trench, has the first conductivity type, and has a higher impurity concentration than the first low-resistance layer.

Silicon carbide semiconductor device and manufacturing method of same

A semiconductor device including: a trench gate; a trench-bottom protecting layer of a second conductivity type provided in a semiconductor layer of a first conductivity type while contacting a bottom of trenches; and a depletion suppressing layer of the first conductivity type provided between adjacent trench-bottom protecting layers, wherein the depletion suppressing layer includes an intermediate point that is horizontally equidistant to the adjacent trench-bottom protecting layers and is formed of a size to contact neither the trenches nor the trench-bottom protecting layers, and an impurity concentration of the depletion suppressing layer is set higher than an impurity concentration of the semiconductor layer.

Semiconductor device and power conversion device

A gate connection layer () includes a portion placed on an outer trench (TO) with a gate insulating film () being interposed. A first main electrode () includes a main contact (CS) electrically connected to a well region () and a first impurity region () within an active region (), and an outer contact (CO) being spaced away from the active region () and in contact with a bottom face of the outer trench (TO). A trench-bottom field relaxing region () is provided in a drift layer (). A trench-bottom high-concentration region () has an impurity concentration higher than that of the trench-bottom field relaxing region (), is provided on the trench-bottom field relaxing region (), and extends from a position where it faces the gate connection layer () with the gate insulating film () being interposed, to a position where it is in contact with the outer contact (CO) of the first main electrode ().

Growing community of inventors

Tokyo, Japan

Katsutoshi Sugawara