Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Ulsi Engineering Corp.

Other

Katsuro Sasaki

Koichiro Ishibashi

Shuji Ikeda

Toshiaki Yamanaka

Satoshi Meguro

Naotaka Hashimoto

Nobuyuki Moriwaki

Atsuyoshi Koike

Soichiro Hashiba

Isamu Kuramoto

Yutaka Kobayashi

Atsushi Hiraishi

Seigou Yukutake

Shigeru Takahashi

Katsuhiro Shimohigashi

Shoji Hanamura

Takashi Hashimoto

Akihiro Shimizu

Toshiaki Masuhara

Makoto Suzuki

Norio Ohkubo

Sadayuki Morita

Kouichi Nagasawa

Kunihiro Komiyaji

Shigeru Honjo

Kiyotsugu Ueda

Masaaki Kubotera

Toshiro Aoto

Takao Oono

Kiyoo Itoh

Katsutaka Kimura

Toshio Sasaki

Yoshio Sakai

Tomoyuki Ishii

Yoshio Homma

Osamu Minato

Minoru Nagata

Masatoshi Ohtake

Naoki Ozawa

Eiji Takeda

Takashi Nishida

Hidehito Obayashi

Kiyoshi Aiki

Suguru Tachibana

Kazuhiro Kondo

Hideaki Nakamura

Nobuo Hamamoto

Isamu Orita

Hiroshi Kishida

Tadashi Onishi

Hisashi Horikoshi

The present invention provides a circuit, in which a device typified by a PLED element is built into a flip-flop. In this case, a storage node of the device is low leakage. According to the present invention, it is possible to realize a SRAM that has nonvolatility while achieving high-speed operation. It is also possible to realize a flip-flop having the same characteristics. An example of a typical mode of the present invention is a storage circuit characterized by the following: a storage element is a device incorporating: a first path for a carrier; a first mode for storing a charge that generates an electric field where conductivity of the first path is changed; and a barrier structure through which a second carrier moves in response to given voltage so that the second carrier is stored in the first node; and the storage circuit includes a second node, to which information stored in the first node is outputted steadily in a state in which power is supplied. The flip-flop and the SRAM are realized using such a basic circuit.

Storage circuit with layered structure element

In a digital information system for realizing the sale of information or the like having a commercial value in the form of a digital signal, and an audio processor, and signal processor suitably used with the system, when a digital signal is received/delivered, a digital signal source is connected directly to a player for receiving and storing a specified information, which is reproduced by the player independently. A voice interval of a digital audio signal is processed to realize the slow and fast playback. The system includes a data compressor and a data extender of simple configuration. The value of the digital signal received/delivered can be exhibited directly. A selling system is constructed easily, and the player is simple in configuration and easy to operate by anyone. The fast and slow playback are possible without deteriorating the sound quality, and ripples can be greatly reduced against the digital input signal, thereby making possible a faithful data compression of an acoustic signal or the like by a simple configuration. The self-diagnosis function permits the use of a defective memory chip, thereby leading to a very economical system.

Digital information system, digital audio signal processor and signal converter

Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines. The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.

SRAM having load transistor formed above driver transistor

Semiconductor integrated circuit device and process for fabricating the

Herein disclosed is a semiconductor integrated circuit device comprising an SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs, and a method of forming this device. The gate electrodes of the drive MISFETs and of the transfer MISFETs of the memory cell, and the word lines, are individually formed of different conductive layers. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The source line is formed of a conductive layer identical to that of the word line. An oxidation resisting film is formed on the gate electrodes of the drive MISFETs so as to reduce stress caused by oxidization of edge portions of these gate electrodes, and to reduce a resulting leakage current. A thickness of an oxide film formed on gate electrodes of the transfer MISFETs and word lines is thicker than an oxide film formed on gate electrodes of the drive MISFETs, so that data line pads can be formed in self-alignment with the oxide film and side wall spacers on the gate electrodes of the transfer MISFETs.

Process for fabricating a semiconductor integrated circuit device

A method is provided for manufacturing a semiconductor integrated circuit device which includes a capacitor element having a first electrode, a second electrode, and a dielectric film formed between said first electrode and said second electrode. In particular, the method includes the step of forming at least one of the first electrode and second electrode with a polycrystalline silicon film which is deposited over a semiconductor substrate by a CVD method and which is doped with an impurity during said deposition to decrease the resistance of the polycrystalline silicon film. The capacitor element formed by this method is particularly useful for memory cells of static random access memory devices.

A semiconductor static memory device, which has an increased storage capacity without imposing an increased access time, includes first, second and third metallic layers. To begin, word lines for the transfer MOSFETS are formed of the same polysilicon layer used to form the gate electrodes of the transfer MOSFETs of the memory device. A metallic layer of the first layer is used for local word lines, with the polysilicon word lines and local word lines being connected at their ends or inside of cell arrays. A metallic layer of the second layer is used for bit layers, and a metallic layer of the third layer is used for main word lines. Consequently, the word lines have a decreased time constant, allowing fast memory access. Each of sense amplifiers used in the memory device are formed with MOSFETs, which are disposed divisionally in adjacent locations. Preferably the gate electrodes of the divided MOSFETs are located symmetrically. In this case, the offset voltage of the sense amplifiers decreases significantly.

Semiconductor memory device having a large storage capacity and a high

Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially. The two transfer MISFETs of the memory cell have their individual gate electrodes connected-with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.

Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.

A method of fabricating semiconductor integrated circuits with an improved yield rate is realized, which requires no special circuits for selecting normal circuit blocks. Removable temporary wires are connected to circuit blocks, which are thus tested. After removing the temporary wires, a plurality of normally-operating circuit blocks are interconnected by new main wires. The need of a special selecting circuit for replacing defective circuit blocks with normal circuit blocks is eliminated without increasing the delay time due to redundancy. The freedom of the main wiring formed after removal of the temporary wires is so high that the functional freedom of the system constructed is improved.

Method of fabricating integrated circuit with improved yield rate

A carry look ahead circuit includes a first circuit for generating a logical sum of inputs, a second circuit for generating a logical product of the inputs, and a selection circuit for selecting either one of an output of the first circuit and an output of the second circuit in accordance with a carry signal from a lower figure to produce the selected output as a carry signal. Consequently, the number of circuit elements can be reduced greatly to configure the high speed and low power consumption carry look ahead circuit.

Carry look ahead circuit

Semiconductor memory device

A MOSFET Static Random Access Memory (SRAM) cell has a symmetrical construction, with a pair of word lines. The word lines are in second level polysilicon, so that they may overlap the driving transistor gates which are in first level polysilicon.

SRAM with dual word lines overlapping drive transistor gates

In a semiconductor memory, a latch circuit is arranged between the outputs of a sense amplifier and the inputs of a data output buffer. First pass-gates are arranged between the outputs of the sense amplifier and the latch circuit, while second pass-gates are arranged between the latch circuit and the inputs of the data output buffer. The outputs of the sense amplifier are transmitted to the inputs of the data output buffer through signal paths which bypass the first pass-gates, the latch circuit and the second pass-gates, whereby the data output buffer generates a data output quickly. Thereafter, the first pass-gates and the second pass-gates are controllably brought to a signal-through condition, whereby the output information items of the sense amplifier are stored in the latch circuit. The data output buffer holds the data output in conformity with the stored information items of the latch circuit. For a period of time for which the data output buffer holds the data output, the sense amplifier is held in a non-activated condition, so that the power consumption of the semiconductor memory is lowered.

High speed semiconductor memory having a direct-bypass signal path

Growing community of inventors

Fuchuu, Japan

Katsuro Sasaki