International Business Machines Corporation

Globalfoundries Inc.

Katsunori Onishi

Shreesh Narasimha

Paul S Chang

Balaji Kannan

Jian Yu

Bala S Haran

Ruilong Xie

Geng Wang

Kern Rim

Chengwen Pei

Paul Christian Parries

Guowei Xu

Suraj Kumar Patil

Yaocheng Liu

Chih-Chiang Chang

Pei Liu

Tao Chu

Vishal Chhabra

Ayse M Ozbek

Toshiharu Furukawa

Oleg Gluschenkov

Zhijiong Luo

Michael Patrick Chudzik

Renee Tong Mo

Vimal Kumar Kamineni

Karen A Nummy

Ashima B Chakravarti

Keith Howard Tabakman

Tek Po Rinus Lee

Ishtiaq Ahsan

Akihisa Sekiguchi

Paul Daniel Kirsch

Anthony I-Chih Chou

Byoung Hun Lee

Bidan Zhang

Kristen Scheer

Ravi K Dasaka

Heemyoung Park

Ahmed Nayaz Noemaun

Andrew Alexander McKnight

The present disclosure relates to semiconductor structures and, more particularly, to replacement metal gate structures and methods of manufacture. The structure includes at least one short channel device including a dielectric material, a workfunction metal, and a capping material, and a long channel device comprising the dielectric material, the workfunction metal and fluorine free gate conductor material.

Short channel and long channel devices

The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.

Cut inside replacement metal gate trench to mitigate N-P proximity effect

A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal.

Integration scheme for gate height control and void free RMG fill

A method includes forming a first plurality of gate structures. A second plurality of gate structures is formed. A first spacer is formed on each of the first and second pluralities of gate structures. A first cavity is defined between the first spacers of a first pair of the first plurality of gate structures. A second cavity is defined between the first spacers of a second pair of the second plurality of gate structures. A second spacer is selectively formed in the second cavity on the first spacer of each of the gate structures of the second pair without forming the second spacer in the first cavity. A first contact is formed contacting the first spacers in the first cavity. A second contact is formed contacting the second spacers in the second cavity.

Method for forming a protection device having an inner contact spacer and the resulting devices

A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type device and a second type device. The method further includes lowering the source and drain regions for the first type device, while protecting the source and drain regions for the second type device. The method further includes performing silicide processes to form silicide regions on the lowered source and drain regions for the first type device and the source and drain regions for the second type device.

Performance optimized gate structures having memory device and logic device, the memory device with silicided source/drain regions that are raised with respect to silicided source/drain regions of the logic device

Method of forming performance optimized gate structures by silicidizing lowered source and drain regions

A stressor structure is formed within a drain region of an access transistor in a dynamic random access memory (DRAM) cell in a semiconductor-on-insulator (SOI) substrate without forming any stressor structure in a source region of the DRAM cell. The stressor structure induces a stress gradient within the body region of the access transistor, which induces a greater leakage current at the body-drain junction than at the body-source junction. The body potential of the access transistor has a stronger coupling to the drain voltage than to the source voltage. An asymmetric etch of a gate dielectric cap, application of a planarization material layer, and a non-selective etch of the planarization material layer and the gate dielectric cap can be employed to form the DRAM cell.

Asymmetric stressor DRAM

The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a junction butting region using low energy ion implantation to reduce parasitic leakage and body-to-body leakage between adjacent FETs that share a common contact in high density memory technologies, such as dynamic random access memory (DRAM) devices and embedded DRAM (eDRAM) devices. A method disclosed may include forming a junction butting region at the bottom of a trench formed in a semiconductor on insulator (SOI) layer using low energy ion implantation and protecting adjacent structures from damage from ion scattering using a protective layer.

Low energy ion implantation of a junction butting region

Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutional following re-crystallization to maximize the tensile stress imparted on channel region. The gate stack is capped during carbon implantation so the risk of carbon entering the gate stack and degrading the conductivity of the gate polysilicon and/or damaging the gate oxide is essentially eliminated. Thus, the carbon implant regions can be formed deeper. Deeper S/D carbon implants which are completely amorphized and then re-crystallized provide greater tensile stress on the n-FET channel region to further optimize electron mobility. Additionally, the gate electrode is uncapped during the n-type dopant process, so the n-type dopant dose in the gate electrode can be at least great as the dose in the S/D regions.

Semiconductor structure and method of forming the structure

A semiconductor defect type determination method and structure. The method includes providing a semiconductor wafer comprising a first field effect transistor (FET) comprising a first type of structure and a second FET comprising a second different type of structure. A first procedure is performed to determine if a first current flow exists between a first conductive layer formed on the first FET and a second conductive layer formed on the first FET. A second procedure is performed to determine if a second current flow exists between a third conductive layer formed the second FET and a fourth conductive layer formed on the second FET. A determination is made from combining results of the first procedure and results of the second procedure that the first FET and the second FET each comprise a specified type of defect.

Semiconductor device defect type determination method and structure

A method of making a semiconductor device includes forming a transistor structure having one of an embedded epitaxial stressed material in a source and drain region and a stressed channel and well, subjecting the transistor structure to plasma oxidation, and removing spacer material from the transistor structure.

Protection of SiGe during etch and clean operations

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Somers, NY, United States of America

Katsunori Onishi