Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Other

Infineon Technologies Ag

Katsuhiko Hoya

Daisaburo Takashima

Tadashi Miyakawa

Hiroyuki Takenaka

Shinichiro Shiratake

Katsuyuki Fujita

Masahiko Nakayama

Kosuke Hatsuda

Kenji Tsuchida

Keisuke Nakatsuka

Akira Katayama

Takashi Nakazawa

Mariko Iizuka

Yoshiaki Osada

Nobert Rehm

Hisaaki Nishimura

Masahiro Takahashi

Takeshi Hamamoto

Yoshihiro Ueda

Takeshi Watanabe

Yukihito Oowaki

Minoru Amano

Ryu Ogiwara

Yasuyuki Eguchi

Hironobu Furuhashi

Yorinobu Fujino

Mikio Miyata

Masashi Kawamura

Nao Matsuoka

Keiichi Ryu

Yasuharu Takagi

Mariko Ilzuka

A semiconductor storage device includes first and second wirings that are in a first layer above the substrate, extend along a first direction, and are adjacent to each other along a second direction, third and fourth wirings that are in a second layer above the first layer, extend along the second direction, and are adjacent to each other along the first direction, first and second memory cells on the first wiring, and a third memory cell on the second wiring. The first to third memory cells each include a variable resistance element and a switching element. The switching element of the first memory cell includes a gate coupled to the third wiring. The switching elements of the second and third memory cells each include a gate coupled to the fourth wiring. The variable resistance elements of the first to third memory cells are formed with equal distances from each other.

Semiconductor storage device including variable resistance elements

According to an embodiment, a semiconductor memory device includes: memory cell arrays; word lines respectively connected to rows of each of the memory cell arrays; bit lines respectively connected to columns of each of the memory cell arrays; row selection circuits provided so as to respectively correspond to the memory cell arrays and connected to the word lines; and column selection circuits provided so as to respectively correspond to the memory cell arrays and connected to the bit lines. When an identical row address is received, the row selection circuits perform selection operations of word lines so that word line lengths from selected memory cells to the row selection circuits vary.

Semiconductor memory device including memory cell arrays

A memory device of one embodiment includes memory elements which store data and parity; a first decoder which, when scrubbing of the data is performed while no external access is being made to the memory device, uses a syndrome generated from the data and the parity to correct an error of a maximum of N bits in a unit of the data; and a second decoder which, when reading of the data is performed, uses the syndrome to correct an error of a maximum of M bits in a unit of the data. The N bits represent the number of bits smaller than the N bits.

Memory device and memory system

A semiconductor storage device includes plural bit lines and plural word lines. The memory cell array has plural memory cells that are connected with the bit lines and word lines, and can store data. Plural sense amplifiers detect the data stored in the memory cells. Plural write drivers write data in the memory cells. A comparison buffer temporarily stores the write data to be written in the memory cells by the write driver. In a series of write sequences, the comparison buffer stores the read data from the memory cells selected as the write object and the write data to be written in the selected memory cells. After a series of write sequences, when the pre-charge command for resetting the voltage of the bit lines is received, the write execution command is executed so that the comparison buffer executes write in the selected memory cells.

Nonvolatile semiconductor storage device equipped with a comparison buffer for reducing power consumption during write

According to one embodiment, a memory device includes a memory cell; a first circuit that performs a first read on the memory cell, writes first data in the memory cell on which the first read has been performed, performs a second read on the memory cell in which the first data has been written, determines data from a result of the first read based on a result of the second read, and writes back the determined data into the memory cell; and an error correcting circuit that performs error correction on the determined data.

Memory device

According to one embodiment, a memory system includes: a first memory cell area where a first memory cell is provided; a second memory cell area where a second memory cell is provided; an ECC circuit which corrects an error of data stored by the first memory cell; and a control circuit which replaces the first memory cell with the second memory cell if the number of times an error is successfully corrected in the first memory cell reaches a first value.

Semiconductor storage device

According to one embodiment, a magnetoresistive memory device includes a substrate having a first surface which includes a first direction; and memory elements each having a switchable resistance. A first column of memory elements lined up along the first direction is different from an adjacent second column of memory elements lined up along the first direction at positions of memory elements in the first direction.

Magnetoresistive memory device

According to one embodiment, a memory includes a magnetoresistive element, a reference cell, a sense amplifier comparing a first current flowing in the magnetoresistive element with a second current flowing in the reference cell, a first transistor having a first control terminal controlling a value of the first current, a second transistor having a second control terminal controlling a value of the second current, and a controller applying a first potential to the first control terminal and a second potential to the second control terminal in a first operation, and applying the first potential to the first control terminal and a third potential larger than the second potential to the second control terminal in a second operation.

Adjustable read reference voltage to reduce errors in memory devices

A magnetoresistive memory device includes a variable resistance element and a read circuit. The resistance element has a resistance state, which is one of switchable first and second resistance states. The first and second resistance states exhibit different resistances. Each of the first and second resistance states is reached by a current flowing through the variable resistance element in one of opposing first and second directions. The read circuit passes a read current through the variable resistance element autonomously in the first or second direction in accordance with the resistance state of the variable resistance element.

A memory according to an embodiment includes bit lines, word lines, source lines, magnetic tunnel junction elements and transistors that are serially connected between the bit lines and the source lines, respectively, and a sense amplifier that detects data stored in the magnetic tunnel junction elements. The semiconductor storage device includes multiplexers between the bit lines and the sense amplifier in order to select one of the bit lines to be connected to the sense amplifier, and write amplifiers that are located corresponding to memory cell blocks each of which includes memory cells each including the magnetic tunnel junction element and the transistor and are connected to the bit lines or connected via the multiplexers to the bit lines. To write data, the sense amplifier applies a write voltage to the bit lines and then the write amplifiers hold the write voltage.

Semiconductor storage device comprising magnetic tunnel junction elements and write amplifiers

According to one embodiment, a semiconductor memory device includes: a first bit line; a first source line; a first word line; a first control line; a first memory cell comprising a first variable resistance element and a first transistor, the first transistor including a gate coupled to the first word line, the first memory cell including one end coupled to the first bit line and another end coupled to the first source line; a second transistor including one end coupled to the first bit line; and a third transistor including a gate coupled to the first control line, one end coupled to the first bit line, and another end coupled to the first source line.

Semiconductor memory device

A semiconductor storage device includes a cell array including resistance change elements formed above a semiconductor substrate; first cell transistors formed on the semiconductor substrate and provided in association with the resistance change elements; first gate electrodes included in the first cell transistor and extending in a first direction; a first bit lines electrically connected to the resistance change elements respectively and extending in a second direction perpendicular to the first direction; a second bit lines electrically connected to one end of a current path of the first cell transistors respectively and extending in the second direction; and first active areas in which the first cell transistors are formed, and which extend in a direction crossing the first direction at a first angle.

According to one embodiment, a semiconductor memory includes a first memory cell stably storing data after a first time from an end of a write operation, a buffer latching the data in the write operation, and a control circuit controlling a first read operation when the first read operation is executed right after the write operation for the first memory cell is executed, where the first read operation is an operation for the first memory cell, and the first read operation is an operation reading the data from the buffer without accessing the first memory cell.

Semiconductor memory capable of reading data without accessing memory cell

According to one embodiment, a semiconductor memory device includes: a first active area provided in a semiconductor substrate; a second active area provided in the semiconductor substrate and intersecting with the first active area; a first select transistor comprising a first drain region provided in the first active area and a source region provided in an intersection region of the first and second active areas; a second select transistor comprising a second drain region provided in the second active area and sharing the source region; a word line coupled to gates of the first and second select transistors; and first and second variable resistance elements coupled to the first and second drain regions, respectively.

According to one embodiment, a semiconductor memory device includes a first memory circuit and a first controller. The first memory circuit includes a register in which a read page size is stored, and a memory cell array. The first controller is configured to access the first memory circuit by the page size stored in the register, in one of an open page policy and closed page policy.

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Yokohama, Japan

Katsuhiko Hoya