International Business Machines Corporation

Kathleen A Perry

William L Guthrie

William J Patrick

Charles L Standley

John Edward Cronin

Klaus D Beyer

Jacob Riseman

Carter W Kaanta

Rangaswamy Srinivasan

Bodil E Braren

Barbara Jean Luther

William A Pliskin

Paul M Schaible

Stanley R Makarewicz

Eric Mendel

Karen H Brown

Alvin Sugerman

Melanie M Chow

A method for providing superior fill of features in semiconductor processing utilizes a laser ablation system. Deposition is obtained by ablating target materials which are driven off perpendicular to the target in the direction of the deposition surface. The method provides complete fill of high aspect ratio features with nominal heating of the substrate. Alloys and graded layers, as well as pure metals, can be deposited in low temperature patterned layers. In addition, the system has been used to achieve superior trench filling for isolation structures.

Deposition method for high aspect ratio features using photoablation

A method is disclosed for producing coplanar metal/insulator films on a substrate according to a chem-mech polishing technique. In one example, a substrate having a patterned insulating layer of dielectric material thereon, is coated with a layer of metal. The substrate is then placed in a parallel polisher and the metal is removed elsewhere except in the holes where it is left intact. This is made possible through the use of an improved selective slurry which removes the metal much faster than the dielectric material. The insulating layer may then be used as an automatic etch stop barrier. In a second example a substrate having a patterned metallic layer is coated with an insulating layer and then subjected to chem-mech polishing. The structure is coplanarized by the chem-mech removal of the insulating material from the high points of the structure at a faster rate than from the lower points. Optional etch stop layers also may be used.

Chem-mech polishing method for producing coplanar metal/insulator films

Patterned conductive lines are formed simultaneously with stud via connections through an insulation layer to previously formed underlying patterned conductive lines in multilevel VLSI chip technology. A first planarized layer of insulation is deposited over a first level of patterned conductive material to which contacts are to be selectively established. The first layer then is covered by an etch stop material. Contact holes are defined in the etch stop material at locations where stud connectors are required. The first layer of insulation is not etched at this time. Next, a second planarized layer of insulation, is deposited over the etch stop material. The second layer insulation, in turn, is etched by photolithography down to the etch stop material to define desired wiring channels, some of which will be in alignment with the previously formed contact holes in the etch stop material. In those locations where the contact holes are exposed, the etching is continued into the first layer of insulation to uncover the underlying first level of patterned conductive material. The channels and via holes are overfilled with metallization. The excess metallization is removed by etching or by chem-mech (chemical-mechanical) polishing.

Method for producing coplanar multi-level metal/insulator films on a

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Lagrangeville, NY, United States of America

Kathleen A Perry