Infineon Technologies Ag

International Business Machines Corporation

Siemens Aktiengesellschaft

Karl-Peter Pfefferl

Toshiaki Kirihata

Martin Brox

Dominique Savignac

Jean-Marc Dortu

Garbiel Daniel

Helmut Schneider

Robert Kaiser

Thoai-Thai Le

Martin Gall

Athanasia Chrysostomides

Andrea Trunk

The invention features a method for reading and storing a binary memory cell signal where a signal transit time of the binary memory cell signal between one memory cell and an output terminal is reduced. The method includes applying a binary memory cell signal to a bit line pair; switching through the binary memory cell signal from the bit line pair to a local data line pair via a sense amplifier; switching through the amplified binary memory cell signal by a main data switching unit from the local data line to a main data line pair; and outputting the amplified, transferred binary memory cell signal via the first main data line and the second main data line pairs.

Method for reading and storing binary memory cells signals and circuit arrangement

A memory configuration includes a central connection area. The central connection area is surrounded annularly by cell arrays having memory cells. The memory configuration has compact external dimensions and is suitable, in particular, for a side ratio of 2:1. All the peripheral circuits are preferably disposed in the central connection area. As a result, the propagation time differences between the peripheral circuits and the various cell arrays are relatively small.

Memory configuration with a central connection area

The segmented word line architecture has two master word lines, to which sub-word lines are alternately allocated. Two memory banks can thus be alternately assigned to the sub-word lines.

Segmented word line architecture for dividing up a word line into a plurality of banks for cell arrays having long bit lines

The semiconductor memory of the random access type has data lines, which can be connected to the local data lines in the memory cell array. The data lines are combined in groups and at least one group or individual data lines of the groups are formed by redundant data lines. Input/output lines lead from the memory in groups. A bus system organized in two planes is provided. The first plane is provided with bus lines which can be connected to all of the input/output lines, on the one hand, and to all of the data lines, on the other hand. The second plane has a plurality of individual partial buses, whose bus lines can be connected to in each case all of the data lines of at least two groups of data lines, on the one hand, and to all of the input/output lines of in each case one group, on the other hand.

Semiconductor memory of the random access type with a bus system organized in two planes

The memory banks of semiconductor memories are activated via memory bank decoders. Two groups of memory banks are actuated via identical memory bank decoders. A predecoder is used to switch between the memory bank decoders. The layout of a memory bank decoder in a memory with a smaller memory capacity can thus be transferred without a change to a memory with a greater memory capacity.

Semiconductor memory with a plurality of memory banks

A memory having an array of memory cells. The array includes a plurality of normal memory cells and a redundant memory cell. A decoder is provided for selecting an addressed one of the normal memory cells in response to an address and a normal condition signal and adapted address the redundant memory cell in response to the address and a fault condition signal. A redundant decoder is provided having an electronically erasable read-only-memory cell. The redundant decoder is adapted to produce the normal condition signal and to convert the normal condition signal into the fault condition signal when such read-only-memory cell is programmed into a fault condition. Each one of the read-only memory cells include a flash memory cell, a ferroelectric memory cell, or other such type of electronically erasable read-only memory cell which is substantially non-volatile and is able to retain its programmed state for a relatively long period of time. With such an arrangement, because the electronically erasable read-only-memory cell is electronically programmable, a defective normal memory cell may be replaced with a redundant memory cell the memory is packaged.

Semiconductor memory having redundancy circuit

A fault-tolerant memory device provided with a variable domain redundancy replacement (VDRR) arrangement is described. The memory device includes: a plurality of primary memory arrays; a plurality of domains having at least portions of one domain common to another domain to form an overlapped domain area, and at least one of the domains overlapping portions of at least two of the primary memory arrays; redundancy units, coupled to each of the domains, for replacing faults contained within each of the domains; control circuitry for directing at least one of the faults within one of the domains to be replaced with the redundancy units, wherein at least one other fault of the one domain is replaced by the redundancy unit coupled to another of the domains, if the at least one other fault is positioned within the overlapped domain area. Each redundancy unit supporting the primary memory arrays includes a plurality of redundant elements. Unlike the conventional fixed domain redundancy replacement scheme, RUs are assigned to at least two variable domains, wherein at least a portion of the domain is common to that of another domain. The VDRR makes it possible to choose the most effective domain, and in particular, a smaller domain for repairing a random fault or a larger domain for repairing a clustered faults.

Variable domain redundancy replacement configuration for a memory device

A method and apparatus for repairing a memory device through a selective domain redundancy replacement (SDRR) arrangement, following the manufacture and test of the memory device. A redundancy array supporting the primary arrays forming the memory includes a plurality of redundancy groups, at least one of which contains two redundancy units. A redundancy replacement is hierarchically realized by a domain that includes a faulty element within the redundancy group, and by a redundancy unit that repairs the fault within the selected domain. SDRR allows a domain to customize the optimum number and size redundancy units according to existing fault distributions, while achieving a substantially saving in real estate, particularly over the conventional flexible redundancy replacement, in term of the number of fuses (10-20%). By combining several types of redundancy groups, each having a different number of redundancy elements, full flexible redundancy replacement can also be achieved. Consequently, this approach compensates for the drawback of existing intra-block replacements, flexible redundancy replacements, and variable domain redundancy replacements, while improving repairability irrespective of the fault distribution within the memory device.

Repairable semiconductor integrated circuit memory by selective

A method of making a fault-tolerant memory device employing a variable domain redundancy replacement (VDRR) arrangement is described. The method includes the steps of: subdividing the memory into a plurality of primary memory arrays; defining a plurality of domains, at least one of the domains having at least a portion common to another domain to form an overlapped domain area, and wherein at least one of the domains overlaps portions of at least two of the primary arrays; allocating redundancy means to each of the domains to replace faults contained within each of the domains; and replacing at least one of the faults within one of the domains with the redundancy means coupled to the one domain, and at least one other fault of the one domain is replaced by the redundancy means coupled to another of the domains, if the at least one other fault is positioned within the overlapped domain area. Each redundancy unit supporting the primary memory arrays includes a plurality of redundant elements. Unlike the conventional fixed domain redundancy replacement scheme, redundancy units are assigned to at least two variable domains, wherein at least a portion of the domain is common to that of another domain. VDRR makes it possible to choose the most effective domain, and in particular, a smaller domain for repairing a random fault or a larger domain for repairing a clustered faults.

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Hohenkirchen, Germany

Karl-Peter Pfefferl