International Business Machines Corporation

Globalfoundries Inc.

Karen P McLaughlin

Charles Leon Arvin

Christopher David Muzzy

Thomas Anthony Wassick

Shaji Farooq

Brian Michael Erwin

Brian W Quinlan

Suryanarayana Kaja

Ekta Misra

Hsichang Liu

Gregg B Monjeau

Kim H Ruffing

Jeffrey P Gambino

Timothy Harrison Daubenspeck

Wolfgang Sauter

Thomas Weiss

David John Russell

Eric D Perfecto

Krystyna Waleria Semkow

Krishna R Tunga

Steven Paul Ostrander

Brian Richard Sundlof

Sarah Huffsmith Knickerbocker

Harry David Cox

Joseph F Maniscalco

Glen Nelson Biggs

Phillip W Palmatier

Paul F Findeis

Victor M Vitek

John Di Santis

Rework and recovery processes generally include application of liquid metal etchant compositions to selectively remove one layer at a time of a solder layer and underball metallurgy multilayer stack including a titanium-based adhesion layer, a copper seed layer, a plated copper conductor layer, and a nickel-based barrier layer. The rework and recovery process can be applied to the dies, wafers, and/or substrate.

Flip chip packaging rework

A module including a first semiconductor device, a second semiconductor device, a bridge support structure and a base substrate. The semiconductor devices each having first bonding pads having a first solder joined with the base substrate and the semiconductor devices each having second and third bonding pads joined to second and third bonding pads on the bridge support structure by a second solder and a third solder, respectively, on the second and third bonding pads; the semiconductor devices positioned adjacent to each other such that the bridge support structure joins to both of the semiconductor devices by the second and third solders wherein the third bonding pads are larger than the second bonding pads and the third bonding pads are at a larger pitch than the second bonding pads.

Bridge support structure

A methodology and associated wafer level assembly of testing crackstop structure designs. The wafer level semiconductor assembly includes: a substrate structure shaped to define a set of horizontal directions; a metallization layer located on top of the substrate structure, with the metallization layer including a crackstop structure formed therein in accordance with a crackstop structure design; and a tensioned layer located on top of the metallization layer, with the tensioned layer being made of material having internal tensile forces oriented in the horizontal directions. The tensile forces promote horizontal direction crack propagation in the metallization layer so that the crackstop structure design can be tested more rigorously and reliably before deciding on the crackstop design structure to put into mass production (which mass produced product would typically not include the tensioned layer).

Determining crackstop strength of integrated circuit assembly at the wafer level

A semiconductor structures includes a contact fabricated utilizing a multi material trench-layer. The multi material trench layer is utilized to form a contact trench and the contact trench is utilized to form the contact therein. The trench-layer includes a lower barrier trench layer and an upper photoprocessing layer. The photoprocessing layer is utilized pattern and form contact trench. The barrier layer protects an electroplating conductive layer utilized in forming the contact from corrosion that may occur during the removal of the photoprocessing layer.

Dual layer stack for contact formation

A method of fabricating a semiconductor device includes forming a passivation layer on a least one capping layer of the semiconductor device, and forming an encapsulant layer on the passivation layer. The method further includes patterning the encapsulant layer to expose a portion of the passivation layer and forming a final via opening in the passivation layer. A conductive material is deposited in the final via opening. The method further includes planarizing the conductive material until reaching a remaining portion of the encapsulant layer such that the conductive material is flush with the encapsulant layer and the passivation layer is preserved.

Semiconductor device including passivation layer encapsulant

Disclosed are a method for metallization during semiconductor wafer processing and the resulting structures. In this method, a passivation layer is patterned with first openings aligned above and extending vertically to metal structures below. A mask layer is formed and patterned with second openings aligned above the first openings, thereby forming two-tier openings extending vertically through the mask layer and passivation layer to the metal structures below. An electrodeposition process forms, in the two-tier openings, both under-bump pad(s) and additional metal feature(s), which are different from the under-bump pad(s) (e.g., a wirebond pad; a final vertical section of a crackstop structure; and/or a probe pad). Each under-bump pad and additional metal feature initially comprises copper with metal cap layers thereon. The mask layer is removed, an additional mask layer is formed and patterned with third opening(s) exposing only the under-bump pad(s) and solder material is deposited on the under-bump pad(s).

Far back end of the line metallization method and structures

A method for preforming electrochemical processes requiring the application of electricity on features of a substrate includes shorting out the features using a shorting layer across connectors to which the features a in electrical communication. Electricity is then applied and the process is performed.

Method of performing processes on features with electricity

A method of performing electrochemistry processes on features and connectors of a substrate includes the application of a shorting layer across the connectors which are in electrical contact with the features, thereby shorting the features and creating an assemblage for which electricity is applied.

An electroetching method for removing excess silver-copper braze material from the edges of I/O pads during the manufacture of chip carriers for microelectronic devices, and the product thereby produced, are disclosed. The disclosed method is preferably self-limiting, such that braze material is preferentially removed from all regions of the assembly. The method is particularly useful for producing a desirable sidewall profile, size, and extent of coverage of the I/O pad for the fillet of braze material surrounding the base of pins in a pin grid array device. Agitation control is important for producing the desired uniformity and profile.

Semiconductor package having etched-back silver-copper braze

An apparatus and a method for its use for plating pin grid array packaging modules, with a fixture capable of simultaneously holding a plurality of said pin grid array modules such that three-dimensional bottom surface metallurgy (BSM) is sealingly protected during plating of top surface metallurgy (TSM).

Apparatus and method for plating pin grid array packaging modules

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Poughkeepsie, NY, United States of America

Karen P McLaughlin