International Business Machines Corporation

Shin-Etsu Chemical Co., Ltd.

Karen Elizabeth Petrillo

Marie Angelopoulos

Wayne Martin Moreau

David Robert Medeiros

Wu-Song S Huang

John Patrick Simons

Edward D Babich

Ekmini Anuja De Silva

Katherina E Babich

David Earle Seeger

James J Bucchignano

David V Horak

Steven J Holmes

Qinghuang Lin

Kurt R Kimmel

Robert Neal Lang

Cody John Murray

Douglas Charles LaTulipe

Charles W Koburger, Iii

Tsutomu Ogihara

Zhenxing Bi

Kim Yang Lee

Seiichiro Tachibana

Nelson M Felix

Indira P Seshadri

Nicole A Saulnier

Ari Aviram

Ranee W Kwong

Ahmad D Katnani

Hao Tang

Christopher Frederick Robinson

Wenjie Li

Herman Russell Wendt

Ranee Wai-Ling Kwong

Alex Richard Hubbard

Christopher Karl Magg

Inna V Babich

Steven A Rishton

Yoshio Kawai

Chi-Chun Liu

Dario Leonardo Goldfarb

John Christopher Arnold

Yongan Xu

Gregory Breyta

Timothy A Brunner

Martin Glodde

Arpan Pravin Mahorowala

Somnath Ghosh

Daniel A Corliss

Dominik Metzler

Thomas Benjamin Faure

Dario Gil

C Richard Guarnieri

Yoshinori Taneda

Dmitriy Shneyder

Romain Lallement

Rie Kikuchi

Andrew T Pomerene

Hiroko Nagai

Jennifer Fullam

Dai Junyan

David E Medeiros

Rotbert N Lang

A photoresist is developed on a semiconductor wafer. The wafer is introduced into a controlled cold temperature environment and is maintained there until inelastic thermal contraction of the developed photoresist material results in reducing the critical dimension (CD) of the photoresist by not less than 10% from its value before exposure to the controlled cold temperature environment. Then the semiconductor wafer is removed from the controlled cold temperature environment.

Reducing line edge roughness and mitigating defects by wafer freezing

A method of manufacturing a semiconductor device is provided. The method includes forming a plurality of metal lines on substrate, forming a sacrificial dielectric material layer between the metal lines, forming a hardmask over at least one of the metal lines, etching at least one of the metal lines that is not covered by the hardmask, treating the sacrificial dielectric material layer to soften the layer. The method also includes removing the treated sacrificial dielectric material layer.

Spin on scaffold film for forming topvia

A method of optimizing a lithographic process for semiconductor fabrication includes determining that a semiconductor wafer experienced a photoresist exposure delay. At least one operating parameter of a post exposure baking process is adjusted based on the semiconductor wafer having experienced the photoresist exposure delay. The post exposure baking process is performed on the semiconductor wafer utilizing the adjusted at least one operating parameter.

Dynamic adjustment of post exposure bake during lithography utilizing real-time feedback for wafer exposure delay

A method for removing photoresist bridging defects includes coating a photoresist layer over a dielectric layer formed over a substrate, applying a first developer that results in formation of one or more photoresist bridging defects, and applying a second developer to remove the one or more photoresist bridging defects. The first developer is an aqueous base developer and the second developer is a reverse tone weak developer (RTWD), the RTWD being a mixture of a first (good) solvent and a second (bad) solvent for the photoresist.

Photoresist bridging defect removal by reverse tone weak developer

The present invention provides a resist multilayer film-attached substrate, including a substrate and a resist multilayer film formed on the substrate, in which the resist multilayer film has an organic resist underlayer film difficultly soluble in ammonia hydrogen peroxide water, an organic film soluble in ammonia hydrogen peroxide water, a silicon-containing resist middle layer film, and a resist upper layer film laminated on the substrate in the stated order. There can be provided a resist multilayer film-attached substrate that enables a silicon residue modified by dry etching to be easily removed in a wet manner with a removing liquid harmless to a semiconductor apparatus substrate and an organic resist underlayer film required in the patterning process, for example, an ammonia aqueous solution containing hydrogen peroxide called SC1, which is commonly used in the semiconductor manufacturing process.

Resist multilayer film-attached substrate and patterning process

An extreme ultraviolet lithography pattern stack, including, an inorganic hardmask layer, an under layer on the inorganic hardmask layer, and a resist layer on the under layer, where the inorganic hardmask layer, under layer, and resist layer have a combined thickness in the range of about 8.5 nm to about 70 nm.

Approach to lowering extreme ultraviolet exposure dose for inorganic hardmasks for extreme ultraviolet patterning

The present invention provides a patterning process, which comprises step of forming a BPSG film on the under layer film by using a composition for forming a coating type BPSG film including a base polymer and an organic compound with a content of 25 parts by mass or more of the organic compound with respect to 100 parts by mass of the base polymer, the base polymer having a silicon containing unit, a boron containing unit and a phosphorus containing unit with a total content of the boron containing unit and the phosphorus containing unit being 10 mol % or more, the organic compound having two or more hydroxyl groups or carboxyl groups per one molecule. There can be provided a patterning process in which a fine mask pattern can be formed on the substrate to be processed by the multilayer resist method, and the residue of the resist under layer film on the mask pattern can be removed cleanly enough to process the substrate to be processed without causing damage to the substrate to be processed and the under layer film.

Patterning process using a boron phosphorus silicon glass film

An article including a microelectronic substrate is provided as an article usable during the processing of the microelectronic substrate. Such article includes a microelectronic substrate having a front surface, a rear surface opposite the front surface and a peripheral edge at boundaries of the front and rear surfaces. The front surface is a major surface of the article. A removable annular edge extension element having a front surface, a rear surface and an inner edge extending between the front and rear surfaces has the inner edge joined to the peripheral edge of the microelectronic substrate. In such way, a continuous surface is formed which includes the front surface of the edge extension element extending laterally from the peripheral edge of the microelectronic substrate and the front surface of the microelectronic substrate, the continuous surface being substantially co-planar and flat where the peripheral edge is joined to the inner edge.

Microelectronic substrate having removable edge extension element

An article including a microelectronic substrate is provided as an article usable during the processing of the microelectronic substrate. Such article includes a microelectronic substrate having a front surface, a rear surface opposite the front surface and a peripheral edge at boundaries of the front and rear surfaces. The front surface is a major surface of the article. A removable annular edge extension element having a front surface, a rear surface and an inner edge extending between the front and rear surfaces has the inner edge joined to the peripheral edge of the microelectronic substrate. In such way, a continuous surface is formed which includes the front surface of the edge extension element and the front surface of the microelectronic substrate, the continuous surface being substantially co-planar and flat where the peripheral edge is joined to the inner edge.

Resist compositions having good footing properties even on difficult substrates are obtained by using a combination of base additives including a room temperature solid base, and a liquid low vapor pressure base. The compositions are especially useful on metal substrates such as chromium-containing layers commonly used in mask-making.

Use of mixed bases to enhance patterned resist profiles on chrome or sensitive substrates

A method of forming an image in a photoresist layer. The method includes, providing a substrate; forming the photoresist layer over the substrate; forming a contamination gettering topcoat layer over the photoresist layer, the contamination gettering topcoat layer including one or more polymers and one or more cation complexing agents; exposing the photoresist layer to actinic radiation through a photomask having opaque and clear regions, the opaque regions blocking the actinic radiation and the clear regions being transparent to the actinic radiation, the actinic radiation changing the chemical composition of regions of the photoresist layer exposed to the radiation forming exposed and unexposed regions in the photoresist layer; and removing either the exposed regions of the photoresist layer or the unexposed regions of the photoresist layer. The contamination gettering topcoat layer includes one or more polymers, one or more cation complexing agents and a casting solvent.

Immersion lithography contamination gettering layer

Multilayered resist structures including bilayer and top surface imaging which utilize tuned underlayers functioning as ARCs, planarizing layers, and etch resistant hard masks whose properties such as optical, chemical and physical properties are tailored to give a multilayer resist structure exhibiting high resolution, residue free lithography and methods of preparing these materials.

Multilayered resist systems using tuned polymer films as underlayers and methods of fabrication thereof

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Voorheesville, NY, United States of America

Karen Elizabeth Petrillo