United Microelectronics Corp.

Kao-Su Huang

Wei-Shiau Chen

Yung-Chang Lin

Chien-Kuo Wang

Ruey-Chyr Lee

Ta-Chuan Yeh

Ni-Min Chung

A substrate is provided having an oxide layer, a first nitride-silicon, a STI, and a second nitride-silicon. A pattern poly-silicon layer on the second nitride-silicon layer is etched to form a deep trench opening. Etching the pattern poly-silicon layer also deepens the deep trench opening. Then, a conductive layer is filled in the deep trench opening.

Method of manufacturing a capacitor deep trench and of etching a deep trench opening

A treatment method for a surface of a photoresist layer is provided. After forming a patterned photoresist layer over a wafer, a surface treatment step is performed to the photoresist layer by using at least one reaction gas comprising hydrogen bromide or hydrogen iodide to form a hardened layer over the surface of the photoresist layer. Wherein, the surface treatment step and the etching step are in-situ performed.

Treatment method for surface of photoresist layer and method for forming patterned photoresist layer

A method for rounding the bottom corners of a trench is described. In the method, an etching process is performed using a fluorocarbon compound with at least two carbon atoms, He and Oas an etching gas to round the bottom corners of the trench.

Method for rounding bottom corners of trench and shallow trench isolation process

A fabrication method for a multi-layered thin film protective layer, which is applicable on a substrate having a peripheral circuit area and a pixel cell area, is described. Metal layers and pixel cells are formed on the peripheral circuit area and the pixel cell area, respectively. A first oxide layer, a silicon nitride layer and a second oxide layer are sequentially formed on the pixel cells and the metal layers. The second oxide layer is then patterned to define a pre-determined position of a pad spacer in the pixel cell area and the peripheral circuit area. The silicon nitride layer and the first oxide layer are further defined to form a first protective layer in the peripheral circuit area and to from a pad spacer in the pixel cell area exposing the pixel cells. A second protective layer is then formed on the exposed pixel cells.

Fabrication method for a multi-layered thin film protective layer

The present invention provides an etching process for decreasing mask defect. The process comprises providing a substrate, and sequentially forming a thin film layer, a mask, and a photoresist on the surface of the substrate. Then the photoresist is trimmed by a bromide compound, and a first etching process is performed to transfer patterns from the photoresist to the mask. A strip process is performed to strip photoresist by mixing gases that include fluorine. Finally, a second etching process is performed to transfer the pattern from patterned mask to the thin film layer.

Etching process for decreasing mask defect

A fabrication method for a multi-layered thin film protective layer which is applicable on a substrate comprising a peripheral circuit area and a pixel cell area is described. Metal layers and pixel cells are formed on the peripheral circuit area and the pixel cell area, respectively, wherein an insulation material is formed in the interspace between the metal layers and between the pixel cells to provide a sufficient separation. Thereafter, a first oxide layer, a silicon nitride layer and a second oxide layer are sequentially formed on the pixel cells and the metal layers. The second oxide layer is then patterned to define a pre-determined position of a pad spacer in the pixel cell area and the peripheral circuit area. The silicon nitride layer and the first oxide layer are further defined to form a first protective layer in the peripheral circuit area and to from a pad spacer in the pixel cell area exposing the pixel cells. A second protective layer is then formed on the exposed pixel cells.

A multi-layered thin film protective layer structure, which is applicable for a liquid crystal display with a substrate comprising a peripheral circuit area and a pixel cell area, is described. The pixel cell area and the peripheral circuit area comprise a plurality of pixel cells and metal layers, respectively. The multi-layered thin film protective layer also includes a protective layer in the peripheral circuit area to cover the metal layers and a plurality of pad spacers in the pixel cell area and the peripheral circuit area. The pad spacers are higher than the first protective layer. The structure also comprises a second protective layer in the pixel cell area to cover the pixel cells, wherein the second protective layer has a higher reflectivity to allow the transmission of light to reach the pixel cells and a reflection of light.

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Tainan Hsien, Taiwan

Kao-Su Huang