International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Stmicroelectronics Gmbh

Elpis Technologies Inc.

Adeia Semiconductor Solutions LLC

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Samsung Electronics Co., Ltd.

Renesas Electronics Corporation

Globalfoundries U.S. Inc.

Globalfoundries U.S. 2 LLC

Tessera LLC

International Business Corporation

Terresa, Inc.

Commissariat À L'énergie Atomique Et Aux Énergies Alternatives

Kangguo Cheng

Ali Khakifirooz

Juntao Li

Alexander Reznicek

Ruilong Xie

Bruce Bennett Doris

Peng Xu

Pouya Hashemi

Xin Miao

Chen Zhang

Veeraraghavan S Basker

Tenko Yamashita

Theodorus E Standaert

Junli Wang

Wenyu Xu

Zhenxing Bi

Karthik Balakrishnan

Geng Wang

Choonghyun Lee

Chanro Park

Ramachandra Divakaruni

Julien Frougier

Ghavam G Shahidi

Heng Wu

Nicolas J Loubet

Shom Ponoth

Chengwen Pei

Shogo Mochizuki

Carl John Radens

Fee Li Lie

Xiuyu Cai

Fei Liu

Chun-chen Yeh

Balasubramanian Pranatharthiharan

Kern Rim

Jack Allan Mandelman

Hong He

Zuoguang Liu

Lawrence Alfred Clevenger

Zheng Xu

Dominic Joseph Schepis

Chih-Chao Yang

Tak H Ning

John H Zhang

Sivananda K Kanakasabapathy

Devendra K Sadana

Reinaldo Ariel Vega

Ying Di Zhang

Soon-Cheon Seo

Jeehwan Kim

William R Tonti

Dechao Guo

Ajey Poovannummoottil Jacob

Keith Kwong Hon Wong

Qing Liu

Terence B Hook

Davood Shahrjerdi

Ruqiang Bao

Takashi Ando

Stephen W Bedell

Haining S Yang

Hemanth Jagannathan

Charles W Koburger, Iii

Brent A Anderson

Toshiharu Furukawa

Oleg Gluschenkov

Min Gyu Sung

Edward J Nowak

Keith E Fogel

Mukta G Farooq

Timothy Joseph Dalton

Huilong Zhu

Louis L Hsu

Steven J Holmes

Son Van Nguyen

Christian Lavoie

Jingyun Zhang

Praneet Adusumilli

Hui Zang

Michael A Guillorn

Judson Robert Holt

Christopher J Penny

Robert Russell Robison

Ekmini Anuja De Silva

Dureseti Chidambarrao

Jed Hickory Rankin

Shu-Jen Han

David V Horak

Qizhi Liu

Isaac Lauer

Takeshi Nogami

John Edward Sheets, Ii

Yanli Zhang

Injo Ok

Oscar Van Der Straten

Michael Patrick Chudzik

Guy M Cohen

Dharmendra S Modha

Josephine B Chang

Michael Rizzolo

A gate-all-around field effect transistor device is provided. The gate-all-around field effect transistor device includes one or more channel layers on a substrate. The gate-all-around field effect transistor device further includes an inner spacer wrapped around four sides of an end portion of each of the one or more channel layers. The gate-all-around field effect transistor device further includes a portion of an inner spacer liner between a portion of an upper most channel layer and a portion of an outer spacer.

Gate-all-around field-effect-transistor with wrap-around-channel inner spacer

An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes a source drain contact above and contacting a source drain region of a semiconductor device. The interconnect structure also includes a via above and contacting the source drain contact. The via includes a lower portion with an uppermost surface that contacts a lowermost surface of an interlayer dielectric.

Liner-less via contact

A phase-change memory device with reduced heater size includes a first conductive structure within a first dielectric layer. A heater element is located within a second dielectric layer disposed above the first conductive structure. The heater element includes a third dielectric layer defining a perimeter, a top portion of a heater material layer partially overlapping the perimeter of the third dielectric layer, and a bottom portion of the heater material layer overlapping the perimeter of the third dielectric layer. The bottom portion of the heater material layer is in contact with the first conductive structure. A phase-change material is located above the heater element with a bottom surface of the phase-change material being in contact with the top portion of the heater material layer. The phase-change memory device further includes a second conductive structure located above the phase-change material.

Phase-change memory cell with reduced heater size

A semiconductor includes a first GAA FET and second GAA FET. The second GAA FET includes a first gate dielectric and second gate dielectric within its gate structure. The first GAA FET includes just the first gate dielectric within its gate structure. The gate dielectric structure of the first GAA FET provides for a nominal or a lesser effective gate dielectric or gate dielectric resistance relative to an effective gate dielectric structure of the second GAA FET. The first GAA FET further includes a first gate conductor within its gate structure and the second GAA FET further includes the first gate conductor and a second gate conductor within its gate structure. The first gate conductor and the second gate conductor are separated by the second gate dielectric.

Heterogeneous gate all around dielectric thickness

A phase change memory includes a phase change structure. There is a heater coupled to a first surface of the phase change structure. A first electrode is coupled to a second surface of the phase change structure. A second electrode coupled to a second surface of the heater. A third electrode is connected to a first lateral end of the phase change structure and a fourth electrode connected to a second lateral end of the phase change structure.

Multi-level programming of phase change memory device

A device structure for a phase-change memory device is disclosed. The device structure includes a top electrode, a phase-change material that is recessed between two layers of resistive liner material, and a conductive material. The conductive material contacts the sidewall of the top electrode, the sidewall of the phase-change material, and a portion of a top surface and a bottom surface of each of the two layers of the resistive liner material. The device structure includes a heater contacting a bottom electrode and the bottom layer of the resistive liner material. The heater is in a first bilayer dielectric. A second bilayer dielectric is under the top electrode.

Phase-change memory device with conductive cladding

A magnetoresistive random access memory (MRAM) device having chip identification using normal operating voltages is provided. No dedicated programming is needed. Instead, programming of the MRAM device is free and random and is a result of providing a magnetic via structure sufficiently close to the magnetic free layer of the magnetic junction tunnel (MTJ) structure such that the magnetic via structure projects a magnetic field that interacts with the magnetic free layer and aligns the magnetization of the magnetic free layer with the magnetization of the magnetic via structure. Thus, the orientation of the magnetization of both the magnetic via structure and the magnetic free layer are aligned in a same direction. The magnetization of the magnetic via structure can thus be used as a physical unclonable function and the MTJ structure can be used to read out this information.

MRAM-based chip identification with free random programming

Embodiments herein describe semiconductor devices with single diffusion breaks that are narrower than the gates of transistors in those devices. That is, rather than forming the diffusion breaks using a dummy gate (which would result in the diffusion breaks having the same width as the gates of the transistors) the embodiments herein use different means to establish the width of the diffusion break. As a result, the diffusion break can be narrower than traditional diffusion breaks formed using dummy gates, thereby saving area in the semiconductor device.

Narrowing single diffusion break

An integrated circuit (IC) is provided. The IC includes a substrate that includes first and second channels. A shared source or drain (S/D) region is between the first and second channels. The shared source or drain region includes an uppermost surface and further includes a second surface recessed from the uppermost surface and sidewalls extending from the uppermost surface to the second surface to define a recess. First and second gate structures including gate metal are disposed on the first and second channels. An S/D wrap-around contact (WAC) includes a first portion which extends into the recess to contact the second surface and the sidewalls and is wrapped around the S/D region at an exterior of the recess.

Non-self-aligned wrap-around contact in a tight gate pitched transistor

A semiconductor structure having a backside contact structure with increased contact area includes a plurality of source/drain regions within a field effect transistor, each of the plurality of source/drain regions includes a top portion having an inverted V-shaped area. A backside power rail is electrically connected to at least one source/drain region through a backside metal contact. The backside metal contact wraps around a top portion of the at least one source/drain region. A tip of the top portion of the plurality of source/drain regions points towards the backside power rail with the top portion of the at least one source/drain region being in electric contact with the backside metal contact. A first epitaxial layer is in contact with a top portion of at least another source/drain region adjacent to the at least one source/drain region for electrically isolating the at least another source/drain region from the backside power rail.

Semiconductor backside contact structure with increased contact area

A semiconductor device includes: a vertical transport field-effect transistor (VTFET) device including a bottom source/drain (S/D) epitaxial layer, a vertical fin channel formed on the bottom S/D epitaxial layer, and a top S/D epitaxial layer formed on the vertical fin channel. The bottom S/D epitaxial layer has an asymmetric profile in cross-section where a first side of the vertical fin channel is aligned with a first side of the bottom S/D epitaxial layer, and the bottom S/D epitaxial layer has a stepped profile that extends beyond a second edge of the vertical fin channel.

VTFET with controlled fin height

A method including forming a plurality of nanosheets on a substrate and forming a plurality of sacrificial layers on the substrate, wherein the plurality of nanosheets and the plurality of sacrificial layers are arranged as alternating layers. Forming and patterning a first hardmask located on top of one of the sacrificial layers and forming a second hardmask around the first hardmask. Patterning the plurality of nanosheets and the plurality of sacrificial layers. Forming and patterning a dummy gate located on top of first hard mask. Removing the plurality of sacrificial layers. Forming a plurality of nanowires, where the plurality of nanowires is formed by the removal of the plurality of sacrificial layers, where the removal of the plurality of sacrificial layers thins sections of each of the plurality of nanowires forming the plurality of nanowires.

Nanowire source/drain formation for nanosheet device

A stacked semiconductor device includes a lower semiconductor device that has a backside and includes a flipped upper semiconductor device that has a backside that is opposed to the lower semiconductor device backside. The flipped upper semiconductor device further includes a backside residual semiconductor on insulator (SOI) layer and a stressed dielectric portion thereupon. The stacked semiconductor device may be formed by stacking and bonding the flipped upper semiconductor device to the lower semiconductor device, removing one or more semiconductor on insulator (SOI) layers from the backside of the flipped upper semiconductor device while retaining an exposed backside residual SOI layer of the flipped upper semiconductor device, forming a stressed dielectric layer upon the exposed backside residual SOI layer, and patterning the stressed dielectric layer.

Vertically stacked FET with strained channel

A buried power rail contact structure is provided that wraps around a source/drain region of a first field effect transistor (FET), contacts a surface of a buried power rail, and has a reduced height as compared to a height of a neighboring source/drain contact structure that contacts a surface of a source/drain region of a second FET. Both the buried power rail contact structure and the source/drain contact structure have a negative taper, i.e., each of the buried power rail contact structure and the source/drain contact structure has outermost sidewalls that slope outward from a topmost surface of the contact structure to a bottommost surface of the contact structure. Such contact structures reduce the parasitic capacitance between a functional gate structure and the contact structure.

Buried power rail with robust connection to a wrap around contact

Semiconductor channel layers vertically aligned and stacked one on top of another, each separated by a gate stack material, a source-drain epitaxy region adjacent to the semiconductor channel layers, a vertical side surface of the source-drain epitaxy region is adjacent to a vertical side surface of a conductive trench contact. A first set and a second set of semiconductor channel layers, a conductive trench contact between them and a source-drain between the first set and the conductive trench contact. Forming a first stack, a second stack and a third stack of nanosheet layers, forming a first, second and third sacrificial gate, forming a first source drain between the first and second stack, forming a second source drain between the second and third, forming a vertical trench in the first source drain while protecting the second source drain, and forming a stressor material layer in the vertical trench.

Strain generation and anchoring in gate-all-around field effect transistors

Growing community of inventors

Albany, NY, United States of America

Kangguo Cheng