International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Stmicroelectronics Gmbh

Elpis Technologies Inc.

Adeia Semiconductor Solutions LLC

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Samsung Electronics Co., Ltd.

Renesas Electronics Corporation

Globalfoundries U.S. Inc.

Globalfoundries U.S. 2 LLC

Tessera LLC

International Business Corporation

Terresa, Inc.

Kangguo Cheng

Ali Khakifirooz

Juntao Li

Alexander Reznicek

Ruilong Xie

Bruce Bennett Doris

Peng Xu

Pouya Hashemi

Xin Miao

Chen Zhang

Veeraraghavan S Basker

Tenko Yamashita

Theodorus E Standaert

Junli Wang

Wenyu Xu

Zhenxing Bi

Karthik Balakrishnan

Geng Wang

Choonghyun Lee

Ramachandra Divakaruni

Chanro Park

Julien Frougier

Ghavam G Shahidi

Heng Wu

Nicolas J Loubet

Shom Ponoth

Chengwen Pei

Shogo Mochizuki

Carl John Radens

Fee Li Lie

Xiuyu Cai

Fei Liu

Chun-chen Yeh

Balasubramanian Pranatharthiharan

Kern Rim

Jack Allan Mandelman

Hong He

Zuoguang Liu

Lawrence Alfred Clevenger

Zheng Xu

Dominic Joseph Schepis

Chih-Chao Yang

Tak H Ning

John H Zhang

Sivananda K Kanakasabapathy

Devendra K Sadana

Reinaldo Ariel Vega

Ying Di Zhang

Soon-Cheon Seo

Jeehwan Kim

William R Tonti

Dechao Guo

Ajey Poovannummoottil Jacob

Keith Kwong Hon Wong

Qing Liu

Terence B Hook

Davood Shahrjerdi

Ruqiang Bao

Takashi Ando

Stephen W Bedell

Haining S Yang

Hemanth Jagannathan

Charles W Koburger, Iii

Brent A Anderson

Toshiharu Furukawa

Oleg Gluschenkov

Edward J Nowak

Keith E Fogel

Mukta G Farooq

Timothy Joseph Dalton

Huilong Zhu

Louis L Hsu

Min Gyu Sung

Steven J Holmes

Son Van Nguyen

Christian Lavoie

Jingyun Zhang

Praneet Adusumilli

Hui Zang

Michael A Guillorn

Judson Robert Holt

Christopher J Penny

Robert Russell Robison

Ekmini Anuja De Silva

Dureseti Chidambarrao

Jed Hickory Rankin

Shu-Jen Han

David V Horak

Qizhi Liu

Isaac Lauer

Takeshi Nogami

John Edward Sheets, Ii

Yanli Zhang

Injo Ok

Oscar Van Der Straten

Michael Patrick Chudzik

Kenneth Parker Rodbell

Dharmendra S Modha

Josephine B Chang

Michael Rizzolo

A method including forming a plurality of nanosheets on a substrate and forming a plurality of sacrificial layers on the substrate, wherein the plurality of nanosheets and the plurality of sacrificial layers are arranged as alternating layers. Forming and patterning a first hardmask located on top of one of the sacrificial layers and forming a second hardmask around the first hardmask. Patterning the plurality of nanosheets and the plurality of sacrificial layers. Forming and patterning a dummy gate located on top of first hard mask. Removing the plurality of sacrificial layers. Forming a plurality of nanowires, where the plurality of nanowires is formed by the removal of the plurality of sacrificial layers, where the removal of the plurality of sacrificial layers thins sections of each of the plurality of nanowires forming the plurality of nanowires.

Nanowire source/drain formation for nanosheet device

A stacked semiconductor device includes a lower semiconductor device that has a backside and includes a flipped upper semiconductor device that has a backside that is opposed to the lower semiconductor device backside. The flipped upper semiconductor device further includes a backside residual semiconductor on insulator (SOI) layer and a stressed dielectric portion thereupon. The stacked semiconductor device may be formed by stacking and bonding the flipped upper semiconductor device to the lower semiconductor device, removing one or more semiconductor on insulator (SOI) layers from the backside of the flipped upper semiconductor device while retaining an exposed backside residual SOI layer of the flipped upper semiconductor device, forming a stressed dielectric layer upon the exposed backside residual SOI layer, and patterning the stressed dielectric layer.

Vertically stacked FET with strained channel

A buried power rail contact structure is provided that wraps around a source/drain region of a first field effect transistor (FET), contacts a surface of a buried power rail, and has a reduced height as compared to a height of a neighboring source/drain contact structure that contacts a surface of a source/drain region of a second FET. Both the buried power rail contact structure and the source/drain contact structure have a negative taper, i.e., each of the buried power rail contact structure and the source/drain contact structure has outermost sidewalls that slope outward from a topmost surface of the contact structure to a bottommost surface of the contact structure. Such contact structures reduce the parasitic capacitance between a functional gate structure and the contact structure.

Buried power rail with robust connection to a wrap around contact

Semiconductor channel layers vertically aligned and stacked one on top of another, each separated by a gate stack material, a source-drain epitaxy region adjacent to the semiconductor channel layers, a vertical side surface of the source-drain epitaxy region is adjacent to a vertical side surface of a conductive trench contact. A first set and a second set of semiconductor channel layers, a conductive trench contact between them and a source-drain between the first set and the conductive trench contact. Forming a first stack, a second stack and a third stack of nanosheet layers, forming a first, second and third sacrificial gate, forming a first source drain between the first and second stack, forming a second source drain between the second and third, forming a vertical trench in the first source drain while protecting the second source drain, and forming a stressor material layer in the vertical trench.

Strain generation and anchoring in gate-all-around field effect transistors

A semiconductor structure includes a backside contact, and an unmerged source/drain region. The backside contact is wrapped-around the unmerged source/drain region.

Semiconductor structure with wrapped-around backside contact

A method of forming a two dimensional (2D) vertical fin is provided. The method includes heat treating a periodic array of irregular openings in a substrate, wherein there are walls of substrate material between adjacent openings, to reduce the surface area of the openings, and etching the openings with a crystal-plane selective etch to form squared openings in the substrate.

Two-dimensional vertical fins

A method is presented for employing a physically unclonable function (PUF) structure for chip authentication. The method includes connecting a plurality of gain cells to either a first multiplexer or a second multiplexer and receiving outputs from the first and second multiplexers by a current sense amplifier. The plurality of gain cells can be either two-transistor gain cell memories or three-transistor gain cell memories.

Gain cell memory based physically unclonable function

A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.

Air gap spacer for metal gates

A stacked phase change memory structure having a cross-point architecture is provided. The stacked phase change memory structure includes at least two phase change material element-containing structures stacked one atop the other. Each phase change material element-containing structure of the plurality of phase change material element-containing structures has a cross-point architecture and includes, from bottom to top, at least one bottom electrode, a phase change material element, and a top electrode.

Stacked cross-point phase change memory

A method including forming a plurality of nanosheet layers on a substrate and forming a plurality of first sacrificial layers on the substrate, wherein the plurality of nanosheet layers and the plurality of first sacrificial layers are arranged in alternating layers, where the plurality of first sacrificial layers is comprised of a first material. Selectively removing the plurality of first sacrificial layers and forming a plurality of second sacrificial layers where the plurality of first sacrificial layers were removed, where the plurality of second sacrificial layers is comprised of a second material, where the first material and the second material are different. Recessing the plurality of second sacrificial layers at an even rate.

Method to release nano sheet after nano sheet fin recess

Semiconductor devices, and methods of forming the same, include forming a stack of channel layers, including an upper device region and a lower device region. The upper device region is separated from the lower device region by a dielectric spacer layer. A first work function metal layer is formed on the channel layers in the lower device region. A height of the first work function metal layer does not rise above the dielectric spacer layer. A second work function metal layer is formed on the channel layers in the upper device region.

Work function metal patterning for nanosheet CFETs

Embodiments of the invention include a transistor coupled to a memory element, the memory element being in series with a first bistable resistive element that is configured to switch between a first low resistance state and a first high resistance state. A logic circuit is coupled to the transistor via a series connection to a second bistable resistive element, the second bistable resistive element being configured to switch between a second low resistance state and a second high resistance state.

Circuit architecture using transistors with dynamic dual functionality for logic and embedded memory drivers

A resistive random access memory (ReRAM) device is provided. The ReRAM device includes a first electrode including a first conductive layer sandwiching a second conductive layer, the second conductive layer being wider than the first conductive layer; a resistive switching element layer formed in contact with sidewalls of the first electrode, a first portion of the resistive switching element layer that is in contact with the sidewalls of the first conductive layer having a width that is greater than a second portion of the resistive switching element layer that is in contact with the sidewalls of the second conductive layer; and a second electrode that is in contact with the resistive switching element layer.

Resistive switching memory cell

Semiconductor structures having an increased gate length are provided by providing a vertical stack of suspended semiconductor channel material nanosheets that include a middle portion located between a first end portion and a second end portion. The middle portion of each suspended semiconductor channel material nanosheet is vertically offset from (i.e., higher or lower than) the first end portion and the second end portion of each suspended semiconductor channel material nanosheet.

Increased gate length at given footprint for nanosheet device

A semiconductor chip device includes a substrate with a back end of line layer and a backside power delivery network. An input power line is electrically coupled to the backside power delivery network. Dummy transistors are positioned in a circuit with analog or digital circuit elements. A power gating transistor is positioned in the circuit between the dummy transistors and the analog or digital circuit elements. Power from the power input line is provided from the backside power delivery network, through the dummy transistors, and controlled by the power gating transistor for transfer to the analog or digital circuit elements. The device uses a backside delivery of power to the area of the dummy transistors to transfer power into the analog or digital circuit elements, which leaves more of the front side footprint for functional devices.

Power gating dummy power transistors for back side power delivery networks

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Albany, NY, United States of America

Kangguo Cheng