International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Stmicroelectronics Gmbh

Elpis Technologies Inc.

Adeia Semiconductor Solutions LLC

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Samsung Electronics Co., Ltd.

Renesas Electronics Corporation

Globalfoundries U.S. Inc.

Globalfoundries U.S. 2 LLC

Tessera LLC

International Business Corporation

Terresa, Inc.

Kangguo Cheng

Ali Khakifirooz

Juntao Li

Alexander Reznicek

Ruilong Xie

Bruce Bennett Doris

Peng Xu

Pouya Hashemi

Xin Miao

Chen Zhang

Veeraraghavan S Basker

Tenko Yamashita

Theodorus E Standaert

Junli Wang

Wenyu Xu

Zhenxing Bi

Karthik Balakrishnan

Geng Wang

Choonghyun Lee

Ramachandra Divakaruni

Chanro Park

Julien Frougier

Ghavam G Shahidi

Heng Wu

Nicolas J Loubet

Shom Ponoth

Chengwen Pei

Shogo Mochizuki

Carl John Radens

Fee Li Lie

Xiuyu Cai

Fei Liu

Chun-chen Yeh

Balasubramanian Pranatharthiharan

Kern Rim

Jack Allan Mandelman

Hong He

Zuoguang Liu

Lawrence Alfred Clevenger

Zheng Xu

Dominic Joseph Schepis

Chih-Chao Yang

Tak H Ning

John H Zhang

Sivananda K Kanakasabapathy

Devendra K Sadana

Reinaldo Ariel Vega

Ying Di Zhang

Soon-Cheon Seo

Jeehwan Kim

William R Tonti

Dechao Guo

Ajey Poovannummoottil Jacob

Keith Kwong Hon Wong

Qing Liu

Terence B Hook

Davood Shahrjerdi

Ruqiang Bao

Takashi Ando

Stephen W Bedell

Haining S Yang

Hemanth Jagannathan

Charles W Koburger, Iii

Brent A Anderson

Toshiharu Furukawa

Oleg Gluschenkov

Edward J Nowak

Keith E Fogel

Mukta G Farooq

Timothy Joseph Dalton

Huilong Zhu

Louis L Hsu

Steven J Holmes

Min Gyu Sung

Son Van Nguyen

Christian Lavoie

Jingyun Zhang

Praneet Adusumilli

Hui Zang

Michael A Guillorn

Judson Robert Holt

Christopher J Penny

Robert Russell Robison

Ekmini Anuja De Silva

Dureseti Chidambarrao

Jed Hickory Rankin

Shu-Jen Han

David V Horak

Qizhi Liu

Isaac Lauer

Takeshi Nogami

John Edward Sheets, Ii

Yanli Zhang

Injo Ok

Michael Patrick Chudzik

Oscar Van Der Straten

Kenneth Parker Rodbell

Dharmendra S Modha

Josephine B Chang

Michael Rizzolo

A method of forming a two dimensional (2D) vertical fin is provided. The method includes heat treating a periodic array of irregular openings in a substrate, wherein there are walls of substrate material between adjacent openings, to reduce the surface area of the openings, and etching the openings with a crystal-plane selective etch to form squared openings in the substrate.

Two-dimensional vertical fins

A method is presented for employing a physically unclonable function (PUF) structure for chip authentication. The method includes connecting a plurality of gain cells to either a first multiplexer or a second multiplexer and receiving outputs from the first and second multiplexers by a current sense amplifier. The plurality of gain cells can be either two-transistor gain cell memories or three-transistor gain cell memories.

Gain cell memory based physically unclonable function

A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.

Air gap spacer for metal gates

A stacked phase change memory structure having a cross-point architecture is provided. The stacked phase change memory structure includes at least two phase change material element-containing structures stacked one atop the other. Each phase change material element-containing structure of the plurality of phase change material element-containing structures has a cross-point architecture and includes, from bottom to top, at least one bottom electrode, a phase change material element, and a top electrode.

Stacked cross-point phase change memory

A method including forming a plurality of nanosheet layers on a substrate and forming a plurality of first sacrificial layers on the substrate, wherein the plurality of nanosheet layers and the plurality of first sacrificial layers are arranged in alternating layers, where the plurality of first sacrificial layers is comprised of a first material. Selectively removing the plurality of first sacrificial layers and forming a plurality of second sacrificial layers where the plurality of first sacrificial layers were removed, where the plurality of second sacrificial layers is comprised of a second material, where the first material and the second material are different. Recessing the plurality of second sacrificial layers at an even rate.

Method to release nano sheet after nano sheet fin recess

Semiconductor devices, and methods of forming the same, include forming a stack of channel layers, including an upper device region and a lower device region. The upper device region is separated from the lower device region by a dielectric spacer layer. A first work function metal layer is formed on the channel layers in the lower device region. A height of the first work function metal layer does not rise above the dielectric spacer layer. A second work function metal layer is formed on the channel layers in the upper device region.

Work function metal patterning for nanosheet CFETs

Embodiments of the invention include a transistor coupled to a memory element, the memory element being in series with a first bistable resistive element that is configured to switch between a first low resistance state and a first high resistance state. A logic circuit is coupled to the transistor via a series connection to a second bistable resistive element, the second bistable resistive element being configured to switch between a second low resistance state and a second high resistance state.

Circuit architecture using transistors with dynamic dual functionality for logic and embedded memory drivers

A resistive random access memory (ReRAM) device is provided. The ReRAM device includes a first electrode including a first conductive layer sandwiching a second conductive layer, the second conductive layer being wider than the first conductive layer; a resistive switching element layer formed in contact with sidewalls of the first electrode, a first portion of the resistive switching element layer that is in contact with the sidewalls of the first conductive layer having a width that is greater than a second portion of the resistive switching element layer that is in contact with the sidewalls of the second conductive layer; and a second electrode that is in contact with the resistive switching element layer.

Resistive switching memory cell

Semiconductor structures having an increased gate length are provided by providing a vertical stack of suspended semiconductor channel material nanosheets that include a middle portion located between a first end portion and a second end portion. The middle portion of each suspended semiconductor channel material nanosheet is vertically offset from (i.e., higher or lower than) the first end portion and the second end portion of each suspended semiconductor channel material nanosheet.

Increased gate length at given footprint for nanosheet device

A semiconductor chip device includes a substrate with a back end of line layer and a backside power delivery network. An input power line is electrically coupled to the backside power delivery network. Dummy transistors are positioned in a circuit with analog or digital circuit elements. A power gating transistor is positioned in the circuit between the dummy transistors and the analog or digital circuit elements. Power from the power input line is provided from the backside power delivery network, through the dummy transistors, and controlled by the power gating transistor for transfer to the analog or digital circuit elements. The device uses a backside delivery of power to the area of the dummy transistors to transfer power into the analog or digital circuit elements, which leaves more of the front side footprint for functional devices.

Power gating dummy power transistors for back side power delivery networks

A method for forming a semiconductor device includes forming a structure having at least a first nanosheet stack for a first device, a second nanosheet stack for a second device and disposed over the first nanosheet stack, a disposable gate structure, and a gate spacer. The disposable gate structure and sacrificial layers of the first and second nanosheet stacks are removed thereby forming a plurality of cavities. A conformal gate dielectric layer is formed in the plurality cavities and surrounding at least portions of the first and second nanosheet stacks. A first conformal work function layer is formed in contact with the gate dielectric layer. Portions of the first conformal work function layer are removed without using a mask from at least the second nanosheet stack. A second conformal work function layer is formed on exposed portions of the gate dielectric layer.

Vertical stacked nanosheet CMOS transistors with different work function metals

Embodiments herein describe FETs with channels connected on the sides to a metal liner. To avoid the difficulties of connecting the sides of the channels to metal liners for the drain and source regions, the embodiments herein form a male/female contact between the channels and the metal liners. In one embodiment, instead of exposing only the end or side surfaces of the channels, an end knob of the channel is exposed. This knob can include the side surface as well as a portion of the top, bottom, front, and back sides of the channel. As such, when the metal liner is deposited on the knob, this metal forms an electrical connection on all sides of the knob. This male/female connection provides a more reliable and lower resistance connection between the channel and the metal liner than using only the end or side surfaces of the channel.

Wrap-around-contact for 2D-channel gate-all-around field-effect-transistors

FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.

FinFET devices

The density of deuterium or hydrogen within phase change material (PCM) of a PCM memory cell reduces the active defects in the amorphous phase of the PCM by passivating dangling bonds, which results in the PCM becoming easier to nucleate during the SET process of the PCM memory cell. Resultingly, the addition of deuterium or hydrogen within the PCM relatively increases the SET programming voltage window of the PCM memory cell compared with a similar PCM cell without.

Phase change material including deuterium

Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

Bulk nanosheet with dielectric isolation

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Albany, NY, United States of America

Kangguo Cheng