Kabushiki Kaisha Toshiba

Sony Corporation

Sony Semiconductor Solutions Corporation

Sony Group Corporation

Toshiba Memory Corporation

Kan Shimizu

Toshihiko Hayashi

Satoru Wakiyama

Takuya Nakamura

Keishi Inoue

Naoki Jyo

Naohiko Kimizuka

Jun Ogi

Yuri Kato

Kohei Kinoshita

Yoshihisa Matoba

Takeshi Sasaki

Hitoshi Shiga

Ryuichi Fujimoto

Shigehito Saigusa

Tooru Arai

Makoto Morimoto

Tokihisa Kaneguchi

Yumi Takada

Akira Masuko

Yoshimasa Adachi

Motoki Nagata

A solid-state imaging device that includes a first substrate, one or multiple second substrates, a first wiring layer, a second wiring layer, and a first alignment part. The first substrate includes a first semiconductor substrate with multiple photoelectric conversion sections, and a multilayer wiring layer. The one or multiple second substrates are attached to the first substrate with the multilayer wiring layer interposed therebetween. The first wiring layer is in the multilayer wiring layer and includes multiple first thin metal wires formed at substantially the same first pitches. The second wiring layer is stacked above the first wiring layer in the multilayer wiring layer and includes multiple second thin metal wires formed between the multiple first thin metal wires at substantially the same second pitches in a plan view. The first alignment part is formed above the second wiring layer in the multilayer wiring layer.

Solid-state imaging device

To achieve decreased noise and improved sensitivity by reducing parasitic capacitance in a charge detection sensor. The charge detection sensor includes a detection element, a detection electrode, and a contact. The detection element is provided on one surface of a semiconductor substrate and detects a charge. The detection electrode is provided on another surface different from the one surface of the semiconductor substrate. The contact penetrates the semiconductor substrate and electrically connects the detection electrode and the detection element. Since no wiring layer is formed between the detection element and the detection electrode, the parasitic capacitance is reduced.

Charge detection sensor and potential measurement system

An imaging device includes a first semiconductor element including at least one bump pad that has a concave shape. The at least one bump pad includes a first metal layer and a second metal layer on the first metal layer. The imaging device includes a second semiconductor element including at least one electrode. The imaging device includes a microbump electrically connecting the at least one bump pad to the at least one electrode. The microbump includes a diffused portion of the second metal layer, and first semiconductor element or the second semiconductor element includes a pixel unit.

Semiconductor device and method of manufacturing the same

There is provided semiconductor devices and methods of forming the same, the semiconductor devices including: a first semiconductor element having a first electrode; a second semiconductor element having a second electrode; a Sn-based micro-solder bump formed on the second electrode; and a concave bump pad including the first electrode opposite to the micro-solder bump, where the first electrode is connected to the second electrode via the micro-solder bump and the concave bump pad.

Semiconductor device and method of manufacturing thereof

A light emitting element and display device are disclosed. In one example, a light emitting element includes a first electrode formed on a base body. A first insulation layer is formed on the base body and the first electrode and has an aperture portion in which a part of the first electrode is exposed. A second insulation layer is formed on the first insulation layer and has a protruding end portion protruding from the aperture portion. A third insulation layer is formed on the second insulation layer and has an end portion recessed from the protruding end portion. A charge injection/transport layer is formed over the second insulation layer and the third insulation layer. An organic layer includes a light emitting layer, and a second electrode formed on the organic layer. At least a part of the charge injection/transport layer is discontinuous at the protruding end portion.

Light emitting element and display device

It is possible to reduce resistance variations of a member connecting a through-silicon via to a line and improve wiring reliability. A hole through which the through-silicon via is to be stretched is created and an over-etching process is carried out on a wiring layer including the line. Then, by embedding copper in the hole, the through-silicon via made of the copper can be created. After the through-silicon via has been connected to the line made of aluminum through the member which is a connection area, the connection area is alloyed in a thermal treatment in order to electrically connect the through-silicon via to the line. Thus, it is possible to reduce variations of a resistance between the through-silicon via and the line and also improve wiring reliability as well. The present technology can be applied to a semiconductor device and a method for manufacturing the semiconductor device.

Semiconductor device and semiconductor-device manufacturing method

According to one embodiment, a semiconductor memory device includes: a word line; a first memory cell; a first circuit; and a second circuit. The first memory cell is connected to the word line. The first circuit generates a first voltage having a waveform including a first time period during which a voltage value increases with time and a second time period during which the voltage value decreases with time, and applies the generated first voltage to the word line. The second circuit measures first time from a first timing when a state of the first memory cell changes according to the first voltage to a second timing when the state of the first memory cell changes according to the first voltage after the first timing. The second circuit determines first data stored in the first memory cell on the basis of the measured first time.

Read process in a semiconductor memory device including a memory cell transistor

Growing community of inventors

Tokyo, Japan

Kan Shimizu