International Business Machines Corporation

Globalfoundries Inc.

Kamal Kumar Sikka

Hilton T Toy

Jeffrey Allen Zitz

Paul F Bodenweber

Shidong Li

Sushumna Iruvanti

Dinesh Gupta

Fee Li Lie

Dario Leonardo Goldfarb

Krishna R Tunga

Daniel A Corliss

Kenneth Charles Marston

Jiantao Zheng

Ravi K Bonam

Joshua M Rubin

Donald Francis Canaperi

Evan G Colgan

Thomas Weiss

Jon Alfred Casey

Virendra R Jadhav

Jamil A Wakil

Randall Jason Werner

Kathryn C Rivera

Maryse Cournoyer

Chenzhou Lian

David L Questad

Steven Paul Ostrander

Tuhin Sinha

Lawrence Alfred Clevenger

Michael A Gaynes

Charles Leon Arvin

Arvind Kumar

Govindarajan Natarajan

David L Edwards

Xiaojin Wei

Mark William Kapfhammer

Iqbal Rashid Saraf

Jeffrey Thomas Coffin

Gregg B Monjeau

Marcus E Interrante

Suresh D Kadakia

Martin Beaumier

Paul Stephen Andry

Jeffrey Donald Gelorme

Raschid Jose Bezama

Katsuyuki Sakuma

Steven Lorenz Wright

Hiroyuki Mori

James John Kelly

Kevin R Winstel

Amilcar R Arvelo

Yang Liu

Steve Ostrander

Dale Curtis McHerron

Taryn J Davis

Pascale Gagnon

Valérie Anne Oberson

Piyas Bal Chowdhury

Kathryn R Lange

William John Starke

John Ulrich Knickerbocker

Ramachandra Divakaruni

Mukta G Farooq

Alfred Grill

Gerald Keith Bartley

Rudy J Wojtecki

Marc Adam Bergendahl

Babar Ali Khan

Benjamin V Fasano

Gregory Breyta

Vijayeshwar Das Khanna

Teddie Peregrino Magbitang

Subhash Laxman Shinde

James N Humenik

Thomas Edward Lombardi

Peter Jeffrey Brofman

John Harold Magerlein

Anson Jay Call

Raed A Sherif

Brian W Quinlan

Hsichang Liu

Yi Pan

Isabel De Sousa

Richard D Langlois

David R Motschman

Wei Zou

Christian Bergeron

Catherine Dufort

Michael J Emmett

Charles C Bureau

Rui Wang

Dishit Paresh Parekh

Mohamed Belazzouz

A chip package comprises a chip having a first temperature sensor. The first temperature sensor is configured to measure a first temperature of the chip in a localized area around the first temperature sensor. The chip package also includes a chip carrier coupled to the chip via a plurality of solder connections. The chip carrier includes a second temperature sensor vertically aligned with the first temperature sensor. The second temperature sensor is configured to measure a second temperature of the chip carrier in a localized area around the second temperature sensor. The chip carrier further includes a localized heater element located near the second temperature sensor and configured to generate heat in response to a detected difference based on comparison of the first temperature and the second temperature such that the detected difference is adjusted in the localized area around the first temperature sensor.

Fatigue failure resistant electronic package

A composition, process, and device are disclosed. The composition includes a polymer formed by reacting an epoxy compound with an amine curing agent. The epoxy compound comprises a Diels-Alder dimer and an ester moiety. The process includes providing a polymer formed by reacting the epoxy compound with the amine curing agent. The device includes a material that includes the polymer.

Rehealable and reworkable polymer for electronic packaging

A flip chip device and methods for fabrication are provided. An interconnect layer for a device include a plurality of solder bumps arranged within the interconnect layer. A first subset of the plurality of solder bumps has a first cross-sectional area, where the first subset is arranged along a first position at a first edge of the interconnect layer. A second subset of the plurality of solder bumps has a second cross-sectional area, where the second subset is arranged at a second position of the interconnect layer. A third subset of the plurality of solder bumps is arranged between the first position and the second position, where the third subset has a plurality of cross-sectional areas.

Electronic package with varying interconnects

An electronic structure includes offset three-dimensional stacked chips; and a two-piece lid structure configured to extract heat from the bottom and top of the stacked chips.

Electronic package structure with offset stacked chips and top and bottom side cooling lid

An electronic device console includes a console body that houses a chip package, and a duct extending from the console body. An interior volume of the duct is in fluid communication with an interior volume of the console body. A first vent is at a distal end of the duct. A second vent is in a wall of the console body. The console may be oriented in a first orientation and a second orientation. The duct functions as a chimney for natural convection cooling of the chip package when the console is oriented in the first orientation. The console body functions as a chimney for natural convection cooling of the chip package when the console is oriented in the second orientation.

Electronic device console with natural draft cooling

A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.

Direct bonded heterogeneous integration silicon bridge

In some examples, an electronic package and methods for forming the electronic package are described. The electronic package can be formed by disposing an interposer on a surface of a substrate having a first pitch wiring density. The interposer can have a second pitch wiring density different from the first pitch wiring density. A layer of non-conductive film can be situated between the interposer and the surface of the substrate. A planarization process can be performed on a surface of the substrate. A solder resist patterning can be performed on the planarized surface the substrate. A solder reflow and coining process can be performed to form a layer of solder bumps on top of the planarized surface of the substrate. The interposer can provide bridge connection between at least two die disposed above the substrate. Solder bumps under the interposer electrically connect the substrate and the interposer.

Circuit substrate with mixed pitch wiring

The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.

Three-dimensional microelectronic package with embedded cooling channels

A heat spreader is disclosed with regions where material is absent to reduce the mass/weight of the heat spreader without substantially reducing the temperature of the semiconductor chip and without substantially affecting the warpage and mechanical stress/strain in the electronic package.

Optimized weight heat spreader for an electronic package

A technique relates to an electronic package. A substrate is configured to receive a chip. A stiffener is attached to the substrate. The stiffener includes a core material with a first material formed on opposing sides of the core material.

Laminated stiffener to control the warpage of electronic chip carriers

Structural combinations of TIMs and methods of combining these TIMs in semiconductor packages are disclosed. An embodiment forms the structures by selectively metallizing a backside of a semiconductor chip (chip) on chip hot spots, placing a higher performance thermal interface material (TIM) on the metallized hot spots, selectively metalizing an underside of a lid in one or more metalized lid locations, and assembling a lid over the backside of the chip to create an assembly so that metalized lid locations are in contact with the higher performance TIMs. A lower performance TIM fills the region surrounding the higher performance TIM on the underside of the lid enclosing the chips. Disclosed are methods of disposing both solid and dispensable TIMs, curing and not curing the thermal interface, and structures to keep the TIMs in place while assembly the package and compressing dispensable TIMs. Alternative method steps are disclosed, such as: injecting the lower performance TIM through injection holes in a pre-assembled assembly, using solid preform TIMs with cutouts, and using high performance TIM structures that have collapsible rails to prevent lower performance TIM from spilling onto the surface of the higher performance TIM to permit good/bonding.

Hybrid TIMs for electronic package cooling

Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.

Direct bonded heterogeneous integration packaging structures

Techniques are provided for constructing multi-chip package structures. For example, a multi-chip package structure includes a package substrate, an interconnect bridge device, a first chip package, and a second chip package. The first chip package includes a first redistribution layer structure, and a first integrated circuit chip connected to the first redistribution layer structure. The first redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The second chip package includes a second redistribution layer structure, and a second integrated circuit chip connected to the second redistribution layer structure. The second redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The interconnect bridge device includes wiring to provide package-to-package connections between the first and second chip packages.

Multi-chip package structures with discrete redistribution layers

An electronic package and a method of manufacture includes a substrate having an upper surface with a trench formed in a bridge region. First pads are arranged on the upper surface of the substrate, outside of the bridge region, and a bridge is positioned in the trench. A plurality of second pads are arranged on an upper surface of the bridge. A plurality of pillars are electrically coupled to the plurality of second pads. Two or more semiconductor chips are positioned in a side-by-side proximal arrangement overlaying the bridge and the substrate. A first semiconductor chip is joined to the bridge, then a second semiconductor chip is joined to the bridge, followed by attaching the chip-bridge assembly to the substrate with the bridge positioned within the substrate trench. Each of the two or more semiconductor chips have first electrical connections including bumps, and second electrical connections including third pads.

Mixed under bump metallurgy (UBM) interconnect bridge structure

The present invention includes embodiments of a semiconductor package designed to transfer heat from one or more bridges within the package to ambient external to the package in addition to conducting the heat through any semiconductor chips encapsulated within the package. A laminated substrate has one or more horizontal layer heat conduction paths and one or more vertical substrate heat conduction paths. The vertical substrate heat conduction paths collect heat from one or more of the horizontal layer heat conduction paths, and eventually conduct the heat out of the semiconductor package, e.g. into a lid or heat sink.

Laminated circuitry cooling for inter-chip bridges

Growing community of inventors

Poughkeepsie, NY, United States of America

Kamal Kumar Sikka