Taiwan Semiconductor Manufacturing Comp. Ltd.

Kai-Ming Liu

Yao-Jen Hsieh

Shih Hsin Chen

Po-Hsiang Huang

Yi-Kan Cheng

Chin-Chou Liu

Fong-Yuan Chang

Hsien-Hsin Sean Lee

Chin-Her Chien

Cheng-Hung Yeh

Ze-Ming Wu

Chien-Chih Kuo

Chin-Yuan Huang

Kai-Yun Lin

Wei-Yang Lin

Yao-Hsien Tsai

Ming-Huei Tsai

Tai-Yu Wang

You-Jiun Wang

Ming-Ke Tsai

A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.

Package structure and method for forming the same

A method includes operation below: extracting layout patterns that include interconnection layers between a first terminal and a second terminal coupled to the first terminal, in a layout design of a circuit; comparing a first portion of the layout patterns with a first coding portion that specifies a first layout constraint, in which the first portion of the layout patterns is extracted in a sequence starting from the first terminal or to the first terminal; comparing a second portion of the layout patterns with a second coding portion that specifies a second layout constraint, in which the second portion of the layout patterns is extracted in a sequence from the second terminal or to the second terminal; in response to comparisons, initiating fabrication of at least one element of the circuit according to the layout design.

Layout checking system and method

A method includes operation below. At least one portion of layout patterns coupled between a first terminal and a second terminal of a circuit is extracted from a layout design for the circuit. The at least one portion is compared with at least one coding portion, in which the at least one coding portion specifies layout constraints for either the first terminal or the second terminal of the circuit. When the at least one portion meets the at least one coding portion, fabrication of the circuit is initiated according to the layout design.

A method includes the operation below. Groups, indicating layout patterns of interconnection layers, are assigned to a circuit, to determine layout constraints of the circuit. Layout patterns are extracted from a layout design for the circuit. The layout patterns are compared with the layout constraints. Data, indicating the layout design, for fabrication of the circuit are generated in a condition that the layout patterns meet the layout constraints.

A method performed by at least one processor comprises the steps of: generating a layout data of a chip comprising transistors; determining heat-related parameters for the transistors based on the locations thereof in the layout data; generating a netlist data comprising the heat-related parameters; performing a post-layout simulation based on the netlist data; and verifying whether the post-layout simulation meets a design specification.

Method of parameter extraction and system thereof

One or more systems and methods for a cell based hybrid resistance and capacitance (RC) extraction are provided. The method includes generating a layout for a semiconductor arrangement, performing a three-dimensional (3D) RC extraction on a target unit cell to obtain a 3D RC result including a coupling capacitance between unit cells, generating a 3D RC netlist based upon the 3D RC result, performing a 2.5 dimensional (2.5D) RC extraction on a peripheral cell to obtain a 2.5D RC netlist, and combining the 3D RC netlist with the 2.5D RC netlist to create a hybrid RC netlist for the layout. In some embodiments, the hybrid RC netlist is generated by stitching the coupling capacitance for at least one of the target unit cell, a repeating unit cell, or the peripheral cell together. In some embodiments, the 3D RC result for the target unit cell is stitched to the repeating unit cell.

System and method for creating hybrid resistance and capacitance (RC) netlist using three-dimensional RC extraction and 2.5 dimensional RC extraction

Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.

Methods for layout verification for polysilicon cell edge structures in FinFET standard cells using filters

An integrated circuit design method comprises extracting parallel-connected parameters associated with circuit components of an integrated circuit (IC) based on a determination that the circuit components are connected in parallel. The method also comprises generating a parallel netlist that describes the circuit components, the parallel netlist comprising the parallel-connected parameters. The parallel-connected parameters are taken into consideration by a simulation that determines the performance capabilities of the IC.

Integrated circuit design method and apparatus

A method of detecting a parasitic transistor detecting is provided. The method includes extracting several diodes from a selected area, selecting at least one diode pair from the diodes in accordance with signals connected to the diodes, and filtering the at least one diode pair in accordance with a threshold distance to determine whether at least one parasitic transistor is obtained.

Method and computer-readable medium for detecting parasitic transistors by utilizing equivalent circuit and threshold distance

A method includes extracting multiple-patterning group assignment information of one or more layout patterns from a layout design. The layout design corresponds to a circuit design, and the one or more layout patterns corresponding to a node of the circuit design. Whether the extracted multiple-patterning group assignment information is consistent with a set of multiple-patterning group assignment constraints of the node is determined by a hardware processor.

Layout checking system for multiple-patterning group assignment constraints

Methods for layout verification for polysilicon cell edge structures in finFET standard cells using filters

A method for checking the inter-chip connectivity of a three-dimensional (3D) integrated circuit (IC) generally comprises receiving a design file for each of a plurality of chips of the 3D IC and generating a plurality of inter-layer ports to be shared between at least two of the of chips based on the design files for each of the chips. A layout without the share ports for each of the chips based on the design files for each of the chips is generated and a layout versus schematic (LVS) check is conducted for each of the generated layouts by using the identified inter-layer ports.

Method and system for checking the inter-chip connectivity of a three-dimensional integrated circuit

Methods for standard cells using finFET standard cell structures with polysilicon on OD edges. Standard cells are defined using finFET transistors and having gate structures forming a transistor at an intersection with a semiconductor fin. Polysilicon dummy structures are formed on the edges of the active areas or OD areas of the standard cells. In a design flow, a pre-layout netlist schematic for the standard cells includes a three terminal MOS device corresponding to the polysilicon dummy structure on the edges of the standard cell. After an automated place and route process forms a device layout using the standard cells, a post layout netlist is extracted. Where two standard cells abut one another, a single polysilicon dummy structure is formed on the common boundary. A layout versus schematic comparison is then performed comparing the pre-layout netlist and the post-layout netlist to verify the layout obtained. Additional methods are disclosed.

Methods for layout verification for polysilicon cell edge structures in FinFET standard cells

A method includes converting an active region in a layout of an integrated circuit into a fin-based structure that has a fin. The active region belongs to an integrated circuit device, and has a planar layout structure. The method further includes extracting a Resistance-Capacitance (RC) loading of the integrated circuit device using the parameters of the fin-based structure. The steps of converting and extracting are performed by a computer.

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Hsinchu, Taiwan

Kai-Ming Liu