Taiwan Semiconductor Manufacturing Comp. Ltd.

Kai-Ming Ching

Chen-Shien Chen

Yen-Ming Chen

Hsin-Hui Lee

Chia-Fu Lin

Chen-Cheng Kuo

Chao-Yuan Su

Li-Chih Chen

Chih-Hua Chen

Tsung-Ding Wang

Ching-Wen Hsiao

Wen-Hsiang Tseng

Chen Chen-Shien

Ta-Min Lin

Sheng-Liang Pan

Bo-I Lee

Yen-Huei Chen

Jiun Yi Wu

Shu-Shen Yeh

Ming Hung Tseng

Kuo-Ching Hsu

Shun-Liang Hsu

Chien-Hsiun Lee

Wen-Chang Kuo

Kuo-Liang Lu

Shih-Cheng Chang

Hui-Chang Yu

Dean Wang

Ming-Hong Tseng

Tung-Heng Shie

Yue-Ying Jian

Jin-Lien Lin

Yu-Min Cheng

Wen-Chih Chiou

Shang-Yun Hou

Chien-Hsun Lee

Han-Ping Pu

Chien-Hung Chen

Chien-Hung Zordius Chen

Yih-Ann Lin

Hon-Lin Huang

Clinton Chao

Hsiu-Mei Yu

Yu-Kung Hsiao

Han-Hsiang Huang

Bai-Yao Lou

Li-Hsin Tseng

Szu-Yao Wang

Ta-Yang Lin

Hao-Wei Chang

Li-Chen Chen

Ding-Chung Lu

Li-Chi Chen

Kuo-Ching “Steven” Hsu

C W Hsiao

Kuo-Ching Lee

Chia-Tsun Hsu

Fang-Chung Liu

Chun-Hong Chang

Chia Fu Lin

A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.

Semiconductor package and method of manufacturing the same

An integrated circuit structure includes a die including a semiconductor substrate, dielectric layers over the semiconductor substrate, an interconnect structure including metal lines and vias in the dielectric layers, a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers, and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.

Cooling channels in 3DIC stacks

System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate.

Through silicon via bonding structure

An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.

A method and system of stacking and aligning a plurality of integrated circuits. The method includes the steps of providing a first integrated circuit having at least one funnel-shaped socket, providing a second integrated circuit, aligning at least one protrusion on the second integrated circuit with the at least one funnel-shaped socket, and bonding the first integrated circuit to the second integrated circuit. The system includes a first integrated circuit having at least one funnel-shaped socket, a metallization-diffusion barrier disposed on the interior of the funnel-shaped socket, and a second integrated circuit. The at least one funnel-shaped socket is adapted to receive a portion of the second integrated circuit.

System and method for 3D integrated circuit stacking

A method of fabricating a semiconductor device including providing a substrate having a front surface and a back surface. A masking element is formed on the front surface of the substrate. The masking element includes a first layer having a first opening and a second layer having a second opening of a greater width than the first opening. The second opening is a tapered opening. The method further includes etching a tapered profile via extending from the front surface to the back surface of the substrate using the formed masking element.

Through-substrate via for semiconductor device

An integrated circuit structure includes a semiconductor chip including a front surface and a back surface; a via extending from the back surface of the semiconductor chip into the semiconductor chip, wherein the via is light transparent; and a photon detector in the semiconductor chip and exposed to the via.

Optical clock signal distribution using through-silicon vias

A new method is provided for the creation of a solder bump. Conventional methods are initially followed, creating a patterned layer of Under Bump Metal over the surface of a contact pad. A layer of photoresist is next deposited, this layer of photoresist is patterned and developed creating a resist mask having a T-shape opening aligned with the contact pad. This T-shaped opening is filled with a solder compound, creating a T-shaped layer of solder compound on the surface of the layer of UBM. The layer of photoresist is removed, exposing the created T-shaped layer of solder compound, further exposing the layer of UBM. The layer of UBM is etched using the T-shaped layer of solder compound as a mask. Reflow of the solder compound results in creating a solder ball.

Method to improve bump reliability for flip chip device

An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a substrate; a through-silicon via (TSV) extending into the substrate; a TSV pad spaced apart from the TSV; and a metal line over, and electrically connecting, the TSV and the TSV pad.

Through-silicon vias and methods for forming the same

An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into the semiconductor substrate; a conductor in the opening; and an isolation layer having a vertical portion and a horizontal portion physically connected to each other. The vertical portion is on sidewalls of the opening. The horizontal portion is directly over the interconnect structure. The integrated circuit structure is free from passivation layers vertically between the top IMD and the horizontal portion of the isolation layer.

Structure and process for the formation of TSVs

A method of forming a stacked die structure is disclosed. A plurality of dies are respectively bonded to a plurality of semiconductor chips on a first surface of a wafer. An encapsulation structure is formed over the plurality of dies and the first surface of the wafer. The encapsulation structure covers a central portion of the first surface of the wafer and leaves an edge portion of the wafer exposed. A protective material is formed over the first surface of the edge portion of the wafer.

Method of forming stacked-die packages

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Jhudong, Taiwan

Kai-Ming Ching