Globalfoundries Inc.

Advanced Micro Devices Corporation

Kai Frohberg

Thomas Werner

Frank Feustel

Ralf Richter

Uwe Griebenow

Katrin Reiche

Matthias Schaller

Jens Heinrich

Carsten Peters

Joerg Hohage

Christoph Schwan

Holger S Schuehrer

Heike Berthold

Hartmut Ruelke

Kerstin Ruttloff

Sven Mueller

Matthias Lehr

Torsten Huisinga

Heike Salz

Jan Hoentschel

Peter Moll

Dominik Olligs

Marco Lepper

Heike Scholz

Manfred Horstmann

Martin Mazur

Massud Aminpur

Volker Grimm

Peter Baars

Sven Beyer

Peter Javorka

Rolf Stephan

Frank Jakubowski

Juergen Boemmels

Hans-Juergen Thees

Robert Seidel

Volker Kahlert

Martin Gerhardt

Christof Streck

Patrick Press

Carsten Hartig

Michael Grillberger

Frank Seliger

Tobias Letz

Katja Huy

Dominic Thurmer

Jens Hahn

Joe Bloomquist

Christin Bartsch

Johannes Groschopf

Volker Jaschke

Jana Schlott

Massud A Aminpur

Sven Muehle

Frank Feustal

Daniel Prochnow

Roberto Klinger

Ruo Qing Su

Jochen Klais

Sandra Bau

Roberto Klingler

The present disclosure provides a method of forming a semiconductor device, including a shaping of a gate structure of the semiconductor device such that a spacer removal after silicide formation is avoided and silicide overhang is suppressed. In some aspects of the present disclosure, a method of forming a semiconductor device is provided wherein a gate structure is provided over an active region of a semiconductor substrate, the gate structure including a gate electrode material and sidewall spacers. At least one of the gate electrode material and the sidewall spacers are shaped by applying a shaping process to the gate structure and a silicide portion is formed on the shaped gate structure.

Method of forming a semiconductor device and according semiconductor device

A semiconductor device includes a silicide contact region positioned at least partially in a semiconductor layer, an etch stop layer positioned above the semiconductor layer, and a dielectric layer positioned above the etch stop layer. A contact structure that includes a conductive contact material extends through at least a portion of the dielectric layer and through an entirety of the etch stop layer to the silicide contact region, and a silicide protection layer is positioned between sidewalls of the etch stop layer and sidewalls of the contact structure.

Semiconductor device comprising contact structures with protection layers formed on sidewalls of contact etch stop layers

When forming semiconductor devices with contact plugs comprising protection layers formed on sidewalls of etch stop layers to reduce the risk of shorts, the protection layers may be formed by performing a sputter process to remove material from a contact region and redeposit the removed material on the sidewalls of the etch stop layers.

Methods for forming protection layers on sidewalls of contact etch stop layers

In a metallization system of a complex semiconductor device, metal pillars, such as copper pillars, may be formed in a nail-like configuration in order to reduce the maximum mechanical stress acting on the metallization system while providing a required contact surface for connecting to the package substrate. The nail-like configuration may be obtained on the basis of appropriately configured resist masks.

Metallization system of a semiconductor device including metal pillars having a reduced diameter at the bottom

A method of reducing the impact of FEoL topography on dual stress liner depositions and the resulting device are disclosed. Embodiments include forming a first nitride layer between and over a pFET and an nFET; thinning the first nitride layer; forming a second nitride layer over the first nitride layer; and removing the first and the second nitride layers from over the pFET.

Tensile nitride profile shaper etch to provide void free gapfill

Integrated circuits with close electrical contacts and methods for fabricating such integrated circuits are provided. The method includes forming a first and a second contact in an interlayer dielectric, and forming a recess between the first and second contact. A etch mask is formed overlying the interlayer dielectric, and the etch mask is removed from over a recess mid-point. A center contact is formed in the interlayer dielectric at the recess mid-point.

Integrated circuits with close electrical contacts and methods for fabricating the same

In a replacement gate approach, the semiconductor material of the gate electrode structures may be efficiently removed during a wet chemical etch process, while this material may be substantially preserved in electronic fuses. Consequently, well-established semiconductor-based electronic fuses may be used instead of requiring sophisticated metal-based fuse structures. The etch selectivity of the semiconductor material may be modified on the basis of ion implantation or electron bombardment.

Semiconductor fuses in a semiconductor device comprising metal gates

By integrating a spacer removal process into the sequence for patterning a first stress-inducing material during a dual stress liner approach, the sidewall spacer structure for one type of transistor may be maintained, without requiring additional lithography steps.

Method for selectively removing a spacer in a dual stress liner approach

Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein electrical interconnects between circuit elements based on a buried sublevel metallization may provide improved transistor density. One illustrative method disclosed herein includes forming a contact dielectric layer above first and second transistor elements of a semiconductor device, and after forming the contact dielectric layer, forming a buried conductive element below an upper surface of the contact dielectric layer, the conductive element providing an electrical connection between the first and second transistor elements.

Buried sublevel metallizations for improved transistor density

During a replacement gate approach, the inverse tapering of the opening obtained after removal of the polysilicon material may be reduced by depositing a spacer layer and forming corresponding spacer elements on inner sidewalls of the opening. Consequently, the metal-containing gate electrode material and the high-k dielectric material may be deposited with enhanced reliability.

High-K gate electrode structure formed after transistor fabrication by using a spacer

When forming metal silicide regions, such as nickel silicide regions, in sophisticated transistors requiring a shallow drain and source dopant profile, superior controllability may be achieved by incorporating a silicide stop layer. To this end, in some illustrative embodiments, a carbon species may be incorporated on the basis of an implantation process in order to significantly modify the metal diffusion during the silicidation process. Consequently, an increased thickness of the metal silicide may be provided, while not unduly increasing the probability of creating contact failures.

Embedding metal silicide contact regions reliably into highly doped drain and source regions by a stop implantation

Adhesion of dielectric layer stacks to be formed after completing the basic configuration of transistor elements may be increased by avoiding the formation of a metal silicide in the edge region of the substrate. For this purpose, a dielectric protection layer may be selectively formed in the edge region prior to a corresponding pre-clean process or immediately prior to deposition of the refractory metal. Hence, non-reacted metal may be efficiently removed from the edge region without creating a non-desired metal silicide. Hence, the further processing may be continued on the basis of enhanced process conditions for forming interlayer dielectric materials.

Enhancing adhesion of interlayer dielectric materials of semiconductor devices by suppressing silicide formation at the substrate edge

Disclosed herein are various methods of forming conductive structures, such as conductive lines and vias, using a dual metal hard mask integration technique. In one example, the method includes forming a first layer of insulating material, forming a first patterned metal hard mask layer above the first layer of insulating material, forming a second patterned metal hard mask layer above the first patterned metal hard mask layer, performing at least one etching process through both of the second patterned metal hard mask layer and the first patterned metal hard mask layer to define a trench in the first layer of insulating material and forming a conductive structure in the trench.

Methods of forming conductive structures using a dual metal hard mask technique

In a metallization system of a semiconductor device, a transition via may be provided with an increased degree of tapering by modifying a corresponding etch sequence. For example, the resist mask for forming the via opening may be eroded once or several times in order to increase the lateral size of the corresponding mask opening. Due to the pronounced degree of tapering, enhanced deposition conditions may be accomplished during the subsequent electrochemical deposition process for commonly filling the via opening and a wide trench connected thereto.

Metallization system of a semiconductor device comprising extra-tapered transition vias

In sophisticated semiconductor devices, an efficient stress decoupling may be accomplished between neighboring transistor elements of a densely packed device region by providing a gap or a stress decoupling region between the corresponding transistors. For example, a gap may be formed in the stress-inducing material so as to reduce the mutual interaction of the stress-inducing material on the closely spaced transistor elements. In some illustrative aspects, the stress-inducing material may be provided as an island for each individual transistor element.

Restricted stress regions formed in the contact level of a semiconductor device

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Niederau, Germany

Kai Frohberg