Taiwan Semiconductor Manufacturing Comp. Ltd.

Kai-Fang Cheng

Hsin-Yen Huang

Hai-Ching Chen

Chi-Lin Teng

Tien-I Bao

Hsiao-Kang Chang

Shao-Kuan Lee

Cherng-Shiaw Tsai

Jung-Hsun Tsai

Cheng-Chin Lee

Kuang-Wei Yang

Shau-Lin Shue

Ting-Ya Lo

Hsiaokang Chang

Ying-Hao Kuo

Chun-Hao Tseng

Ming-Hsien Lin

Ming-Han Lee

Chia-Tien Wu

Chien-Hua Huang

Hsin-Ping Chen

Hai-Ching Cheng

Chuan-Pu Chou

An interfacial structure, along with methods of forming such, are described. The structure includes a first interfacial layer having a first dielectric layer, a first conductive feature disposed in the first dielectric layer, and a first thermal conductive layer disposed on the first dielectric layer. The structure further includes a second interfacial layer disposed on the first interfacial layer. The second interfacial layer is a mirror image of the first interfacial layer with respect to an interface between the first interfacial layer and the second interfacial layer. The second interfacial layer includes a second thermal conductive layer disposed on the first thermal conductive layer, a second dielectric layer disposed on the second thermal conductive layer, and a second conductive feature disposed in the second dielectric layer.

Semiconductor device structure and methods of forming the same

An interconnection structure includes a first dielectric layer, a first conductive layer disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer, a second conductive layer disposed in the second dielectric layer in electrical contact with the first conductive layer, a third dielectric layer formed over the second dielectric layer, wherein the third dielectric layer comprises silicon carbon-nitride (SiCN) based material, and a resistor device disposed in the third dielectric layer.

Semiconductor interconnection structures comprising a resistor device and methods of forming the same

A semiconductor structure includes a base structure, a plurality of electrically conductive features disposed on the base structure, and an isolation structure disposed on the base structure. The base structure includes a substrate. The electrically conductive features are spaced apart from each other. The isolation structure includes a first inter-metal dielectric feature extending horizontally to interconnect the electrically conductive features, a first air gap layer disposed in the isolation structure and around the electrically conductive features, and a first sustaining feature extending horizontally to interconnect the electrically conductive features and disposed between the first inter-metal dielectric feature and the first air gap layer. Methods for manufacturing the semiconductor structure are also disclosed.

Semiconductor structure with air gap and method for manufacturing the same

A semiconductor structure is provided. The semiconductor structure includes a substrate and a device region formed over the substrate. The semiconductor structure further includes an interconnect structure formed over the device region and a first passivation layer formed over the interconnect structure. The semiconductor structure also includes a metal pad formed over and extending into the first passivation layer and a second passivation layer formed over the first passivation layer. The second passivation layer includes a thermal conductive material, and the thermal conductivity of the thermal conductive material is higher than 4 W/mK.

Semiconductor structure with improved heat dissipation

A method for manufacturing a semiconductor structure includes: forming a dielectric layer on a base structure; forming a trench in the dielectric layer to expose the base structure; forming a metal contact in the trench; and performing a plurality of first atomic layer deposition (ALD) cycles to form a plurality of first atomic layers which cover the dielectric layer and the metal contact and which serve as an etch stop layer. Each of the first ALD cycles includes: forming a corresponding one of the first atomic layers; and performing a treatment to convert the corresponding first atomic layer into monocrystalline phase at a temperature not greater than 425° C.

Method for manufacturing semiconductor structure with material in monocrystalline phase

A first dielectric layer is formed on a semiconductor structure. The first dielectric layer has a hardness higher than 10 GPa and a dielectric constant in a range between 1.0 and 4.0. A trench is formed in the first dielectric layer. A conductive feature is formed in the trench in contact with the semiconductor structure. A second dielectric layer is formed over the first dielectric layer and the conductive feature. A via structure is formed in the second dielectric layer in contact with the conductive feature.

Semiconductor interconnection structures and methods of forming the same

A semiconductor device includes a substrate, a first conductive feature disposed in a top portion of the substrate, a metal containing layer disposed on the first conductive feature, and a second conductive feature disposed on and through the metal containing layer and in physical contact with the first conductive feature. The metal containing layer includes an M-O—X group, M representing a metal atom, O representing an oxygen atom, and X representing an element other than hydrogen.

Metal oxide composite as etch stop layer

In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.

Thermal interconnect structure for thermal management of electrical interconnect structure

An interconnection structure includes a first dielectric layer, a first conductive feature, a second dielectric layer, a conductive layer, a liner layer, a third dielectric layer, a second conductive feature, and a first capping layer. The first conductive feature is disposed in the first dielectric layer. The second dielectric layer is formed on the first dielectric layer, and the second dielectric layer is in direct contact with the first dielectric layer. The conductive layer is disposed in the second dielectric layer. The liner layer is disposed between the conductive layer and the second dielectric layer. The third dielectric layer is formed on the second dielectric layer. The second conductive feature is disposed in the third dielectric layer. The first capping layer is disposed between the second conductive feature and the third dielectric layer.

Contact structures and methods of forming the same are provided. A contact structure according to the present disclosure includes an etch stop layer (ESL), a first pillar feature and a second pillar feature disposed on the ESL, a metal feature disposed between the first pillar feature and the second pillar feature, the metal feature including a first sidewall, a bottom surface, a second sidewall, and a top surface, a dielectric liner extending continuously from a top surface of the first pillar feature, along the first sidewall, the bottom surface and the second sidewall of the metal feature, and onto a top surface of the second pillar feature, and a gap between the first pillar feature and a portion of the dielectric liner that extends along the first sidewall of the metal feature.

Interconnect structure with low capacitance and high thermal conductivity

A method for manufacturing a semiconductor device having a low-k carbon-containing dielectric layer includes: depositing a low-k carbon-containing dielectric material, which has a carbon content ranging from 16 atomic % to 23 atomic %, using a precursor mixture to form a carbon-containing dielectric layer having a k value ranging from 2.8 to 3.3 and a porosity ranging from 0.03% to 1.0%; forming the carbon-containing dielectric layer into a patterned carbon-containing dielectric layer having a recess therein by etching, the patterned carbon-containing dielectric layer having a porosity ranging from 1.0% to 2.0%; and filling the recess with an electrically conductive material to form an electrically conductive feature in the patterned carbon-containing dielectric layer.

Method for manufacturing semiconductor device having low-k carbon-containing dielectric layer

The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

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Taoyuan, Taiwan

Kai-Fang Cheng